基于SOPC的单通道TDC设计（3）

Taio · 发表于 2019-4-12 10:50

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本帖最后由 Taio 于 2019-4-12 10:56 编辑

基于SOPC的单通道TDC设计（3）

2 软件系统

2.1 System.h

/*

* system.h - SOPC Builder system and BSP software package information

*

* Machine generated for CPU 'cpu' in SOPC Builder design 'audio_nios'

* SOPC Builder design path: E:/eeworld_soc/eeworld3/tdc1000_SoC/audio_nios.sopcinfo

*

* Generated: Tue Jun 02 11:18:56 CST 2015

*/

/*

* DO NOT MODIFY THIS FILE

*

* Changing this file will have subtle consequences

* which will almost certainly lead to a nonfunctioning

* system. If you do modify this file, be aware that your

* changes will be overwritten and lost when this file

* is generated again.

*

* DO NOT MODIFY THIS FILE

*/

/*

* License Agreement

*

* Altera Corporation, San Jose, California, USA.

*

* Permission is hereby granted, free of charge, to any person obtaining a

* copy of this software and associated documentation files (the "Software"),

* to deal in the Software without restriction, including without limitation

* the rights to use, copy, modify, merge, publish, distribute, sublicense,

* and/or sell copies of the Software, and to permit persons to whom the

* Software is furnished to do so, subject to the following conditions:

*

* The above copyright notice and this permission notice shall be included in

* all copies or substantial portions of the Software.

*

* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE

* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING

* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER

* DEALINGS IN THE SOFTWARE.

*

* This agreement shall be governed in all respects by the laws of the State

* of California and by the laws of the United States of America.

*/

#ifndef __SYSTEM_H_

#define __SYSTEM_H_

/* Include definitions from linker script generator */

#include "linker.h"

/*

* CPU configuration

*

*/

#define ALT_CPU_ARCHITECTURE "altera_nios2_gen2"

#define ALT_CPU_BIG_ENDIAN 0

#define ALT_CPU_BREAK_ADDR 0x05100820

#define ALT_CPU_CPU_ARCH_NIOS2_R1

#define ALT_CPU_CPU_FREQ 100000000u

#define ALT_CPU_CPU_ID_SIZE 1

#define ALT_CPU_CPU_ID_VALUE 0x00000000

#define ALT_CPU_CPU_IMPLEMENTATION "fast"

#define ALT_CPU_DATA_ADDR_WIDTH 0x1b

#define ALT_CPU_DCACHE_BYPASS_MASK 0x80000000

#define ALT_CPU_DCACHE_LINE_SIZE 32

#define ALT_CPU_DCACHE_LINE_SIZE_LOG2 5

#define ALT_CPU_DCACHE_SIZE 2048

#define ALT_CPU_EXCEPTION_ADDR 0x05080020

#define ALT_CPU_FLASH_ACCELERATOR_LINES 0

#define ALT_CPU_FLASH_ACCELERATOR_LINE_SIZE 0

#define ALT_CPU_FLUSHDA_SUPPORTED

#define ALT_CPU_FREQ 100000000

#define ALT_CPU_HARDWARE_DIVIDE_PRESENT 0

#define ALT_CPU_HARDWARE_MULTIPLY_PRESENT 1

#define ALT_CPU_HARDWARE_MULX_PRESENT 0

#define ALT_CPU_HAS_DEBUG_CORE 1

#define ALT_CPU_HAS_DEBUG_STUB

#define ALT_CPU_HAS_EXTRA_EXCEPTION_INFO

#define ALT_CPU_HAS_ILLEGAL_INSTRUCTION_EXCEPTION

#define ALT_CPU_HAS_JMPI_INSTRUCTION

#define ALT_CPU_ICACHE_LINE_SIZE 32

#define ALT_CPU_ICACHE_LINE_SIZE_LOG2 5

#define ALT_CPU_ICACHE_SIZE 4096

#define ALT_CPU_INITDA_SUPPORTED

#define ALT_CPU_INST_ADDR_WIDTH 0x1b

#define ALT_CPU_NAME "cpu"

#define ALT_CPU_NUM_OF_SHADOW_REG_SETS 0

#define ALT_CPU_OCI_VERSION 1

#define ALT_CPU_RESET_ADDR 0x05080000

/*

* CPU configuration (with legacy prefix - don't use these anymore)

*

*/

#define NIOS2_BIG_ENDIAN 0

#define NIOS2_BREAK_ADDR 0x05100820

#define NIOS2_CPU_ARCH_NIOS2_R1

#define NIOS2_CPU_FREQ 100000000u

#define NIOS2_CPU_ID_SIZE 1

#define NIOS2_CPU_ID_VALUE 0x00000000

#define NIOS2_CPU_IMPLEMENTATION "fast"

#define NIOS2_DATA_ADDR_WIDTH 0x1b

#define NIOS2_DCACHE_BYPASS_MASK 0x80000000

#define NIOS2_DCACHE_LINE_SIZE 32

#define NIOS2_DCACHE_LINE_SIZE_LOG2 5

#define NIOS2_DCACHE_SIZE 2048

#define NIOS2_EXCEPTION_ADDR 0x05080020

#define NIOS2_FLASH_ACCELERATOR_LINES 0

#define NIOS2_FLASH_ACCELERATOR_LINE_SIZE 0

#define NIOS2_FLUSHDA_SUPPORTED

#define NIOS2_HARDWARE_DIVIDE_PRESENT 0

#define NIOS2_HARDWARE_MULTIPLY_PRESENT 1

#define NIOS2_HARDWARE_MULX_PRESENT 0

#define NIOS2_HAS_DEBUG_CORE 1

#define NIOS2_HAS_DEBUG_STUB

#define NIOS2_HAS_EXTRA_EXCEPTION_INFO

#define NIOS2_HAS_ILLEGAL_INSTRUCTION_EXCEPTION

#define NIOS2_HAS_JMPI_INSTRUCTION

#define NIOS2_ICACHE_LINE_SIZE 32

#define NIOS2_ICACHE_LINE_SIZE_LOG2 5

#define NIOS2_ICACHE_SIZE 4096

#define NIOS2_INITDA_SUPPORTED

#define NIOS2_INST_ADDR_WIDTH 0x1b

#define NIOS2_NUM_OF_SHADOW_REG_SETS 0

#define NIOS2_OCI_VERSION 1

#define NIOS2_RESET_ADDR 0x05080000

/*

* Define for each module class mastered by the CPU

*

*/

#define __ALTERA_AVALON_JTAG_UART

#define __ALTERA_AVALON_NEW_SDRAM_CONTROLLER

#define __ALTERA_AVALON_ONCHIP_MEMORY2

#define __ALTERA_AVALON_PIO

#define __ALTERA_AVALON_SYSID_QSYS

#define __ALTERA_AVALON_TIMER

#define __ALTERA_NIOS2_GEN2

#define __SEG7_IF

/*

* System configuration

*

*/

#define ALT_DEVICE_FAMILY "Cyclone V"

#define ALT_ENHANCED_INTERRUPT_API_PRESENT

#define ALT_IRQ_BASE NULL

#define ALT_LOG_PORT "/dev/null"

#define ALT_LOG_PORT_BASE 0x0

#define ALT_LOG_PORT_DEV null

#define ALT_LOG_PORT_TYPE ""

#define ALT_NUM_EXTERNAL_INTERRUPT_CONTROLLERS 0

#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1

#define ALT_NUM_INTERRUPT_CONTROLLERS 1

#define ALT_STDERR "/dev/jtag_uart"

#define ALT_STDERR_BASE 0x5101028

#define ALT_STDERR_DEV jtag_uart

#define ALT_STDERR_IS_JTAG_UART

#define ALT_STDERR_PRESENT

#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"

#define ALT_STDIN "/dev/jtag_uart"

#define ALT_STDIN_BASE 0x5101028

#define ALT_STDIN_DEV jtag_uart

#define ALT_STDIN_IS_JTAG_UART

#define ALT_STDIN_PRESENT

#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"

#define ALT_STDOUT "/dev/jtag_uart"

#define ALT_STDOUT_BASE 0x5101028

#define ALT_STDOUT_DEV jtag_uart

#define ALT_STDOUT_IS_JTAG_UART

#define ALT_STDOUT_PRESENT

#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart"

#define ALT_SYSTEM_NAME "audio_nios"

/*

* altera_hostfs configuration

*

*/

#define ALTERA_HOSTFS_NAME "/mnt/host"

/*

* altera_ro_zipfs configuration

*

*/

#define ALTERA_RO_ZIPFS_BASE 0x0

#define ALTERA_RO_ZIPFS_NAME "/mnt/rozipfs"

#define ALTERA_RO_ZIPFS_OFFSET 0x100000

/*

* din32 configuration

*

*/

#define ALT_MODULE_CLASS_din32 altera_avalon_pio

#define DIN32_BASE 0x4000050

#define DIN32_BIT_CLEARING_EDGE_REGISTER 0

#define DIN32_BIT_MODIFYING_OUTPUT_REGISTER 0

#define DIN32_CAPTURE 0

#define DIN32_DATA_WIDTH 32

#define DIN32_DO_TEST_BENCH_WIRING 0

#define DIN32_DRIVEN_SIM_VALUE 0

#define DIN32_EDGE_TYPE "NONE"

#define DIN32_FREQ 10000000

#define DIN32_HAS_IN 1

#define DIN32_HAS_OUT 0

#define DIN32_HAS_TRI 0

#define DIN32_IRQ -1

#define DIN32_IRQ_INTERRUPT_CONTROLLER_ID -1

#define DIN32_IRQ_TYPE "NONE"

#define DIN32_NAME "/dev/din32"

#define DIN32_RESET_VALUE 0

#define DIN32_SPAN 16

#define DIN32_TYPE "altera_avalon_pio"

/*

* hal configuration

*

*/

#define ALT_MAX_FD 32

#define ALT_SYS_CLK TIMER

#define ALT_TIMESTAMP_CLK TIMER

/*

* jtag_uart configuration

*

*/

#define ALT_MODULE_CLASS_jtag_uart altera_avalon_jtag_uart

#define JTAG_UART_BASE 0x5101028

#define JTAG_UART_IRQ 0

#define JTAG_UART_IRQ_INTERRUPT_CONTROLLER_ID 0

#define JTAG_UART_NAME "/dev/jtag_uart"

#define JTAG_UART_READ_DEPTH 64

#define JTAG_UART_READ_THRESHOLD 8

#define JTAG_UART_SPAN 8

#define JTAG_UART_TYPE "altera_avalon_jtag_uart"

#define JTAG_UART_WRITE_DEPTH 64

#define JTAG_UART_WRITE_THRESHOLD 8

/*

* key configuration

*

*/

#define ALT_MODULE_CLASS_key altera_avalon_pio

#define KEY_BASE 0x4000080

#define KEY_BIT_CLEARING_EDGE_REGISTER 0

#define KEY_BIT_MODIFYING_OUTPUT_REGISTER 0

#define KEY_CAPTURE 1

#define KEY_DATA_WIDTH 4

#define KEY_DO_TEST_BENCH_WIRING 0

#define KEY_DRIVEN_SIM_VALUE 0

#define KEY_EDGE_TYPE "FALLING"

#define KEY_FREQ 10000000

#define KEY_HAS_IN 1

#define KEY_HAS_OUT 0

#define KEY_HAS_TRI 0

#define KEY_IRQ 1

#define KEY_IRQ_INTERRUPT_CONTROLLER_ID 0

#define KEY_IRQ_TYPE "EDGE"

#define KEY_NAME "/dev/key"

#define KEY_RESET_VALUE 0

#define KEY_SPAN 16

#define KEY_TYPE "altera_avalon_pio"

/*

* onchip_memory2 configuration

*

*/

#define ALT_MODULE_CLASS_onchip_memory2 altera_avalon_onchip_memory2

#define ONCHIP_MEMORY2_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0

#define ONCHIP_MEMORY2_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0

#define ONCHIP_MEMORY2_BASE 0x5080000

#define ONCHIP_MEMORY2_CONTENTS_INFO ""

#define ONCHIP_MEMORY2_DUAL_PORT 0

#define ONCHIP_MEMORY2_GUI_RAM_BLOCK_TYPE "AUTO"

#define ONCHIP_MEMORY2_INIT_CONTENTS_FILE "audio_nios_onchip_memory2"

#define ONCHIP_MEMORY2_INIT_MEM_CONTENT 1

#define ONCHIP_MEMORY2_INSTANCE_ID "NONE"

#define ONCHIP_MEMORY2_IRQ -1

#define ONCHIP_MEMORY2_IRQ_INTERRUPT_CONTROLLER_ID -1

#define ONCHIP_MEMORY2_NAME "/dev/onchip_memory2"

#define ONCHIP_MEMORY2_NON_DEFAULT_INIT_FILE_ENABLED 0

#define ONCHIP_MEMORY2_RAM_BLOCK_TYPE "AUTO"

#define ONCHIP_MEMORY2_READ_DURING_WRITE_MODE "DONT_CARE"

#define ONCHIP_MEMORY2_SINGLE_CLOCK_OP 0

#define ONCHIP_MEMORY2_SIZE_MULTIPLE 1

#define ONCHIP_MEMORY2_SIZE_VALUE 320000

#define ONCHIP_MEMORY2_SPAN 320000

#define ONCHIP_MEMORY2_TYPE "altera_avalon_onchip_memory2"

#define ONCHIP_MEMORY2_WRITABLE 1

/*

* pio_led configuration

*

*/

#define ALT_MODULE_CLASS_pio_led altera_avalon_pio

#define PIO_LED_BASE 0x4000070

#define PIO_LED_BIT_CLEARING_EDGE_REGISTER 0

#define PIO_LED_BIT_MODIFYING_OUTPUT_REGISTER 0

#define PIO_LED_CAPTURE 0

#define PIO_LED_DATA_WIDTH 10

#define PIO_LED_DO_TEST_BENCH_WIRING 0

#define PIO_LED_DRIVEN_SIM_VALUE 0

#define PIO_LED_EDGE_TYPE "NONE"

#define PIO_LED_FREQ 10000000

#define PIO_LED_HAS_IN 0

#define PIO_LED_HAS_OUT 1

#define PIO_LED_HAS_TRI 0

#define PIO_LED_IRQ -1

#define PIO_LED_IRQ_INTERRUPT_CONTROLLER_ID -1

#define PIO_LED_IRQ_TYPE "NONE"

#define PIO_LED_NAME "/dev/pio_led"

#define PIO_LED_RESET_VALUE 0

#define PIO_LED_SPAN 16

#define PIO_LED_TYPE "altera_avalon_pio"

/*

* rd_empt configuration

*

*/

#define ALT_MODULE_CLASS_rd_empt altera_avalon_pio

#define RD_EMPT_BASE 0x4000020

#define RD_EMPT_BIT_CLEARING_EDGE_REGISTER 0

#define RD_EMPT_BIT_MODIFYING_OUTPUT_REGISTER 0

#define RD_EMPT_CAPTURE 0

#define RD_EMPT_DATA_WIDTH 1

#define RD_EMPT_DO_TEST_BENCH_WIRING 0

#define RD_EMPT_DRIVEN_SIM_VALUE 0

#define RD_EMPT_EDGE_TYPE "NONE"

#define RD_EMPT_FREQ 10000000

#define RD_EMPT_HAS_IN 1

#define RD_EMPT_HAS_OUT 0

#define RD_EMPT_HAS_TRI 0

#define RD_EMPT_IRQ -1

#define RD_EMPT_IRQ_INTERRUPT_CONTROLLER_ID -1

#define RD_EMPT_IRQ_TYPE "NONE"

#define RD_EMPT_NAME "/dev/rd_empt"

#define RD_EMPT_RESET_VALUE 0

#define RD_EMPT_SPAN 16

#define RD_EMPT_TYPE "altera_avalon_pio"

/*

* rd_rqt configuration

*

*/

#define ALT_MODULE_CLASS_rd_rqt altera_avalon_pio

#define RD_RQT_BASE 0x4000030

#define RD_RQT_BIT_CLEARING_EDGE_REGISTER 0

#define RD_RQT_BIT_MODIFYING_OUTPUT_REGISTER 0

#define RD_RQT_CAPTURE 0

#define RD_RQT_DATA_WIDTH 1

#define RD_RQT_DO_TEST_BENCH_WIRING 0

#define RD_RQT_DRIVEN_SIM_VALUE 0

#define RD_RQT_EDGE_TYPE "NONE"

#define RD_RQT_FREQ 10000000

#define RD_RQT_HAS_IN 0

#define RD_RQT_HAS_OUT 1

#define RD_RQT_HAS_TRI 0

#define RD_RQT_IRQ -1

#define RD_RQT_IRQ_INTERRUPT_CONTROLLER_ID -1

#define RD_RQT_IRQ_TYPE "NONE"

#define RD_RQT_NAME "/dev/rd_rqt"

#define RD_RQT_RESET_VALUE 0

#define RD_RQT_SPAN 16

#define RD_RQT_TYPE "altera_avalon_pio"

/*

* sdram configuration

*

*/

#define ALT_MODULE_CLASS_sdram altera_avalon_new_sdram_controller

#define SDRAM_BASE 0x0

#define SDRAM_CAS_LATENCY 3

#define SDRAM_CONTENTS_INFO

#define SDRAM_INIT_NOP_DELAY 0.0

#define SDRAM_INIT_REFRESH_COMMANDS 2

#define SDRAM_IRQ -1

#define SDRAM_IRQ_INTERRUPT_CONTROLLER_ID -1

#define SDRAM_IS_INITIALIZED 1

#define SDRAM_NAME "/dev/sdram"

#define SDRAM_POWERUP_DELAY 100.0

#define SDRAM_REFRESH_PERIOD 15.625

#define SDRAM_REGISTER_DATA_IN 1

#define SDRAM_SDRAM_ADDR_WIDTH 0x19

#define SDRAM_SDRAM_BANK_WIDTH 2

#define SDRAM_SDRAM_COL_WIDTH 10

#define SDRAM_SDRAM_DATA_WIDTH 16

#define SDRAM_SDRAM_NUM_BANKS 4

#define SDRAM_SDRAM_NUM_CHIPSELECTS 1

#define SDRAM_SDRAM_ROW_WIDTH 13

#define SDRAM_SHARED_DATA 0

#define SDRAM_SIM_MODEL_BASE 1

#define SDRAM_SPAN 67108864

#define SDRAM_STARVATION_INDICATOR 0

#define SDRAM_TRISTATE_BRIDGE_SLAVE ""

#define SDRAM_TYPE "altera_avalon_new_sdram_controller"

#define SDRAM_T_AC 6.0

#define SDRAM_T_MRD 3

#define SDRAM_T_RCD 20.0

#define SDRAM_T_RFC 70.0

#define SDRAM_T_RP 20.0

#define SDRAM_T_WR 14.0

/*

* seg7 configuration

*

*/

#define ALT_MODULE_CLASS_seg7 SEG7_IF

#define SEG7_BASE 0x4000000

#define SEG7_IRQ -1

#define SEG7_IRQ_INTERRUPT_CONTROLLER_ID -1

#define SEG7_NAME "/dev/seg7"

#define SEG7_SPAN 32

#define SEG7_TYPE "SEG7_IF"

/*

* sw configuration

*

*/

#define ALT_MODULE_CLASS_sw altera_avalon_pio

#define SW_BASE 0x4000060

#define SW_BIT_CLEARING_EDGE_REGISTER 0

#define SW_BIT_MODIFYING_OUTPUT_REGISTER 0

#define SW_CAPTURE 1

#define SW_DATA_WIDTH 10

#define SW_DO_TEST_BENCH_WIRING 0

#define SW_DRIVEN_SIM_VALUE 0

#define SW_EDGE_TYPE "FALLING"

#define SW_FREQ 10000000

#define SW_HAS_IN 1

#define SW_HAS_OUT 0

#define SW_HAS_TRI 0

#define SW_IRQ 2

#define SW_IRQ_INTERRUPT_CONTROLLER_ID 0

#define SW_IRQ_TYPE "EDGE"

#define SW_NAME "/dev/sw"

#define SW_RESET_VALUE 0

#define SW_SPAN 16

#define SW_TYPE "altera_avalon_pio"

/*

* sysid_qsys configuration

*

*/

#define ALT_MODULE_CLASS_sysid_qsys altera_avalon_sysid_qsys

#define SYSID_QSYS_BASE 0x5101020

#define SYSID_QSYS_ID 0

#define SYSID_QSYS_IRQ -1

#define SYSID_QSYS_IRQ_INTERRUPT_CONTROLLER_ID -1

#define SYSID_QSYS_NAME "/dev/sysid_qsys"

#define SYSID_QSYS_SPAN 8

#define SYSID_QSYS_TIMESTAMP 1433211715

#define SYSID_QSYS_TYPE "altera_avalon_sysid_qsys"

/*

* timer configuration

*

*/

#define ALT_MODULE_CLASS_timer altera_avalon_timer

#define TIMER_ALWAYS_RUN 0

#define TIMER_BASE 0x5101000

#define TIMER_COUNTER_SIZE 32

#define TIMER_FIXED_PERIOD 0

#define TIMER_FREQ 100000000

#define TIMER_IRQ 3

#define TIMER_IRQ_INTERRUPT_CONTROLLER_ID 0

#define TIMER_LOAD_VALUE 99999

#define TIMER_MULT 0.001

#define TIMER_NAME "/dev/timer"

#define TIMER_PERIOD 1

#define TIMER_PERIOD_UNITS "ms"

#define TIMER_RESET_OUTPUT 0

#define TIMER_SNAPSHOT 1

#define TIMER_SPAN 32

#define TIMER_TICKS_PER_SEC 1000

#define TIMER_TIMEOUT_PULSE_OUTPUT 0

#define TIMER_TYPE "altera_avalon_timer"

/*

* wr_full configuration

*

*/

#define ALT_MODULE_CLASS_wr_full altera_avalon_pio

#define WR_FULL_BASE 0x4000040

#define WR_FULL_BIT_CLEARING_EDGE_REGISTER 0

#define WR_FULL_BIT_MODIFYING_OUTPUT_REGISTER 0

#define WR_FULL_CAPTURE 1

#define WR_FULL_DATA_WIDTH 1

#define WR_FULL_DO_TEST_BENCH_WIRING 0

#define WR_FULL_DRIVEN_SIM_VALUE 0

#define WR_FULL_EDGE_TYPE "RISING"

#define WR_FULL_FREQ 10000000

#define WR_FULL_HAS_IN 1

#define WR_FULL_HAS_OUT 0

#define WR_FULL_HAS_TRI 0

#define WR_FULL_IRQ 4

#define WR_FULL_IRQ_INTERRUPT_CONTROLLER_ID 0

#define WR_FULL_IRQ_TYPE "EDGE"

#define WR_FULL_NAME "/dev/wr_full"

#define WR_FULL_RESET_VALUE 0

#define WR_FULL_SPAN 16

#define WR_FULL_TYPE "altera_avalon_pio"

#endif /* __SYSTEM_H_ */

2.2 Main.c

#include "my_includes.h"

#include "LED.h"

#include "SEG7.h"

#include <math.h>

#ifdef DEBUG_APP

#define APP_DEBUG(x) DEBUG(x)

#else

#define APP_DEBUG(x)

#endif

///////////////////////////////////////////////////////////////////////////////

//////////// Internal function prototype & data structure /////////////////////

///////////////////////////////////////////////////////////////////////////////

//================= internal function prototype & data structure definit =====

#define MAX_TRY_CNT 1024

#define USE_SDRAM_FOR_DATA

#ifndef USE_SDRAM_FOR_DATA

#define BUF_SAMPLE_NUM (96000*5) // 5 second @ 96K

#endif

void button_monitor_isr(void* context, alt_u32 id);

bool button_monitor_start(volatile alt_u32 *pPressedMask);

void TDC_monitor_isr(void* context, alt_u32 id);

bool TDC_monitor_start(volatile alt_u32 *pPressedMask);

void TEST_monitor_isr(void* context, alt_u32 id);

bool TEST_monitor_start(volatile alt_u32 *pPressedMask);

void display_time_elapsed(alt_u32 sample_num);

void button_monitor_isr(void* context, alt_u32 id) {

volatile alt_u32* pPressedMask = (volatile alt_u32*) context;

*pPressedMask |= IORD_ALTERA_AVALON_PIO_EDGE_CAP(KEY_BASE) & 0x0F; // 4-button

IOWR_ALTERA_AVALON_PIO_EDGE_CAP(KEY_BASE, 0);

printf("in ISR\r\n");

printf("wr = %d rd = %d \r\n", IORD_ALTERA_AVALON_PIO_DATA(WR_FULL_BASE) & 0x01,

IORD_ALTERA_AVALON_PIO_DATA(RD_EMPT_BASE) & 0x01);

}

bool button_monitor_start(volatile alt_u32 *pPressedMask) {

bool bSuccess = TRUE;

// enable interrupt

IOWR_ALTERA_AVALON_PIO_IRQ_MASK(KEY_BASE, 0x0F); // 4-button

// Reset the edge catpure register

IOWR_ALTERA_AVALON_PIO_EDGE_CAP(KEY_BASE, 0);

printf("in start\r\n");

// register IRQ

if (bSuccess

&& (alt_irq_register(KEY_IRQ, (void *) pPressedMask,

button_monitor_isr) != 0)) {

printf("[SW-MONITOR]register button IRQ fail\r\n");

bSuccess = FALSE;

}

return bSuccess;

}

void TDC_monitor_isr(void* context, alt_u32 id) {

volatile alt_u32* pPressedMask = (volatile alt_u32*) context;

*pPressedMask |= IORD_ALTERA_AVALON_PIO_EDGE_CAP(WR_FULL_BASE) & 0x01; // 1-line in

IOWR_ALTERA_AVALON_PIO_EDGE_CAP(WR_FULL_BASE, 0);

printf("in fifo-ISR\r\n");

}

bool TDC_monitor_start(volatile alt_u32 *pPressedMask) {

bool bSuccess = TRUE;

// enable interrupt

IOWR_ALTERA_AVALON_PIO_IRQ_MASK(WR_FULL_BASE, 0x01); // 4-button

// Reset the edge catpure register

IOWR_ALTERA_AVALON_PIO_EDGE_CAP(WR_FULL_BASE, 0);

printf("in fifo-start\r\n");

// register IRQ

if (bSuccess

&& (alt_irq_register(WR_FULL_IRQ, (void *) pPressedMask,

TDC_monitor_isr) != 0)) {

printf("Fifo IRQ fail\r\n");

bSuccess = FALSE;

}

return bSuccess;

}

void TEST_monitor_isr(void* context, alt_u32 id) {

volatile alt_u32* pPressedMask = (volatile alt_u32*) context;

*pPressedMask |= IORD_ALTERA_AVALON_PIO_EDGE_CAP(TEST_SIG_BASE) & 0x01; // 1-line in

IOWR_ALTERA_AVALON_PIO_EDGE_CAP(TEST_SIG_BASE, 0);

printf("in test-ISR\r\n");

}

bool TEST_monitor_start(volatile alt_u32 *pPressedMask) {

bool bSuccess = TRUE;

// enable interrupt

IOWR_ALTERA_AVALON_PIO_IRQ_MASK(TEST_SIG_BASE, 0x01); // 4-button

// Reset the edge catpure register

IOWR_ALTERA_AVALON_PIO_EDGE_CAP(TEST_SIG_BASE, 0);

printf("in test-start\r\n");

// register IRQ

if (bSuccess

&& (alt_irq_register(TEST_SIG_IRQ, (void *) pPressedMask,

TEST_monitor_isr) != 0)) {

printf("TEST IRQ fail\r\n");

bSuccess = FALSE;

}

return bSuccess;

}

void display_time_elapsed(alt_u32 sample_num) {

// assume sample rate is 48K

alt_u32 time;

SEG7_Decimal(123456, 0x04);

}

bool init(void) {

bool bSuccess = TRUE;

SEG7_Clear();

SEG7_Decimal(0x00000000, 0x00);

return bSuccess;

}

int main() {

volatile alt_u32 button_mask = 0;

volatile alt_u32 tdc_mask = 0;

volatile alt_u32 test_mask = 0;

alt_u32 *pBuf, *pPlaying, *pRecording, RecordLen, PlayLen, data, try_cnt,

buf_sample_size;

printf("\nHello World\n");

if (!init())

return 0;

#ifdef USE_SDRAM_FOR_DATA

pBuf = (alt_u32 *) SDRAM_BASE;

buf_sample_size = SDRAM_SPAN / sizeof(alt_u32);

#else

// alloc memory to stroe PCM data

buf_sample_size = BUF_SAMPLE_NUM;

pBuf = malloc(buf_sample_size * sizeof(alt_u32));

if (!pBuf) {

LCD_TextOut("malloc fail\n\n");

printf("malloc fail\r\n");

return 0;

}

#endif

button_monitor_start(&button_mask); // button IRQ

TDC_monitor_start(&tdc_mask); // TDC IRQ

TEST_monitor_start(&test_mask); // TDC IRQ

printf("ready\n");

// infinite loop

while (1) {

//

}

wu68aq · 发表于 2019-4-12 15:46

本帖最后由 wu68aq 于 2019-4-12 15:48 编辑

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基于SOPC的单通道TDC设计（3）

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