在屏幕上显示大写字母DMH的VGA控制器

Zedd · 发表于 2019-4-11 11:17

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在屏幕上显示大写字母DMH的VGA控制器

基于ise14.7平台，用Nexys3开发板弄了一个显示程序。程序包含六部分

首先是顶层模块：

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company:

// Engineer:

//

// Create Date: 16:04:30 07/22/2015

// Design Name:

// Module Name: vga_initials

// Project Name:

// Target Devices:

// Tool versions:

// Description:

//

// Dependencies:

//

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//

//////////////////////////////////////////////////////////////////////////////////

module vga_initials(

input wire vidon,

input wire[9:0] hc,

input wire[9:0] vc,

input wire[0:31] M,

input wire[7:0] sw,

output wire[3:0] rom_addr4,

output reg[2:0] red,

output reg[2:0] green,

output reg[1:0] blue

);



      parameter hbp=10'b0010010000;//行显示后沿=144（128+16）

      parameter vbp=10'b0000011111;//场显示后沿=31（2+29）

      parameter W=32;

      parameter H=16;



      wire[10:0]C1,R1,rom_addr,rom_pix;

      reg spriteon,R,G,B;

      assign C1={2'b00,sw[3:0],5'b0001};

      assign R1={2'b00,sw[7:4],5'b0001};

      assign rom_addr=vc-vbp-R1;

assign rom_pix =hc-hbp-C1;

      assign rom_addr4=rom_addr[3:0];

      //Enable sprite video out when within the sprite region

      always@(*)

         begin

               if((hc>=C1+hbp)&&(hc<=C1+hbp+W)&&(vc>=R1+vbp)&&(vc<=R1+vbp+H))

                  spriteon=1;

               else

                  spriteon=0;

            end



      //输出彩色信号

      always@(*)

         begin

               red=0;

               green=0;

               blue=0;

               if((spriteon==1)&&(vidon==1))

                  begin

                        R=M[rom_pix];

                              G=M[rom_pix];

                              B=M[rom_pix];

                              red={R,R,R};

                              green={G,G,G};

                              blue={B,B};

                     end

            end

endmodule

然后是子模块1：

module clkdiv(

input wire mclk,

input wire clr,

output wire clk25

);

      reg[1:0]q;



      //2-bit counter

      always@(posedge mclk or posedge clr)

         begin

               if(clr==1)

                  q<=0;

               else

                  q<=q+1'b1;

            end



      assign clk25=q[1];//50MHz  时钟100MHz  （100M/2的1次方）=50MHz

endmodule

子模块2：

module vga_640x480(

input wire clk,

input wire clr,

output reg hsync,

output reg vsync,

output reg[9:0] hc,

output reg[9:0] vc,

output reg vidon

);



      parameter hpixels=10'b1100100000;//行像素点=800



      parameter vlines=10'b1000001001;//行数=521



      parameter hbp=10'b0010010000;//行显示后延=144（128+16）



      parameter hfp=10'b1100010000;//行显示前沿=748（128+16+640）



      parameter vbp=10'b0000011111;//场显示后沿=31（2+29）



      parameter vfp=10'b0111111111;//场显示前延=511（2+29+480）



      reg vsenable;//Enable for the vertical counter



      //行同步信号计数器

      always@(posedge clk or posedge clr)

            begin

                        if(clr==1)

                                 hc<=0;

                              else

                                 begin

                                       if(hc==hpixels-1)

                                          begin

                                                //The counter has reached the end of pixel count

                                                      hc<=0;//计数器复位

                                                      vsenable<=1;

                                                      //Enable the vertical counter to increment

                                             end

                                       else

                                          begin

                                                hc<=hc+1'b1;//Increment the horizontal counter

                                                      vsenable<=0;//Leave the vsenable off

                                          end

                                 end

                              end

      //产生hsync脉冲

      //当hc为0~127时，行同步脉冲为低电平

      always@(*)

      begin

         if(hc<96)

               hsync=0;

               else

               hsync=1;

      end



      //场同步信号计数器

      always@(posedge clk or posedge clr)

      begin

         if(clr==1)

               vc<=0;

               else

               if(vsenable==1)

                        begin

                        if(vc==vlines-1)

                                 //Reset when the number of lines is reached

                                    vc<=0;

                              else

                                 vc<=vc+1'b1;//场计数器+1

                        end

      end



      //产生vsync脉冲

      //当hc为0或1时，场同步脉冲为低电平

      always@(*)

      begin

         if(vc<2)

               vsync=0;

               else

               vsync=1;

      end



      //Enable video out when within the porches

      always@(*)

      begin

         if((hc<hfp)&&(hc>hbp)&&(vc<vfp)&&(vc>vbp))

               vidon=1;

               else

               vidon=0;

      end

endmodule

子模块3：

module vga_initials(

input wire vidon,

input wire[9:0] hc,

input wire[9:0] vc,

input wire[0:31] M,

input wire[7:0] sw,

output wire[3:0] rom_addr4,

output reg[2:0] red,

output reg[2:0] green,

output reg[1:0] blue

);



      parameter hbp=10'b0010010000;//行显示后沿=144（128+16）

      parameter vbp=10'b0000011111;//场显示后沿=31（2+29）

      parameter W=32;

      parameter H=16;



      wire[10:0]C1,R1,rom_addr,rom_pix;

      reg spriteon,R,G,B;

      assign C1={2'b00,sw[3:0],5'b0001};

      assign R1={2'b00,sw[7:4],5'b0001};

      assign rom_addr=vc-vbp-R1;

assign rom_pix =hc-hbp-C1;

      assign rom_addr4=rom_addr[3:0];

      //Enable sprite video out when within the sprite region

      always@(*)

         begin

               if((hc>=C1+hbp)&&(hc<=C1+hbp+W)&&(vc>=R1+vbp)&&(vc<=R1+vbp+H))

                  spriteon=1;

               else

                  spriteon=0;

            end



      //输出彩色信号

      always@(*)

         begin

               red=0;

               green=0;

               blue=0;

               if((spriteon==1)&&(vidon==1))

                  begin

                        R=M[rom_pix];

                              G=M[rom_pix];

                              B=M[rom_pix];

                              red={R,R,R};

                              green={G,G,G};

                              blue={B,B};

                     end

            end

endmodule

子模块四：

module prom_DMH(

input wire[3:0]addr,

      output wire[0:31]M

);

      reg[0:31]rom[0:15];//16个32位寄存器

      parameter data={

         32'b01111110000011000001101000000010,//0

            32'b01000001000011000001101000000010,//1

            32'b01000000100010100010101000000010,//2

            32'b01000000010010100010101000000010,//3

            32'b01000000001010100010101000000010,//4

            32'b01000000001010010100101000000010,//5

            32'b01000000001010010100101000000010,//6

            32'b01000000001010010100101111111110,//7

            32'b01000000001010001000101000000010,//8

            32'b01000000001010001000101000000010,//9

            32'b01000000001010001000101000000010,//10

            32'b01000000001010001000101000000010,//11

            32'b01000000010010000000101000000010,//12

            32'b01000000100010000000101000000010,//13

            32'b01000001000010000000101000000010,//14

            32'b01111110000010000000101000000010//15

      };

      integer i;

      initial

         begin

               for(i=0;i<16;i=i+1)

                  rom=data[(511-32*i)-:32];, W1 R- n% ]# I4 \: i8 W

; s, {( D) V" K* N- i          end
3 G" ]7 b8 d6 g" B  ~/ N8 s+ [8 J! M; M- L* v& ^/ ]! a! i& _% m
      assign M=rom[addr];
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约束文件：7 _: H; E, w  ^" S# W
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Net "mclk" LOC=V10;, e" _6 R6 d9 o
3 C2 t: G( r' H& B; r& n
## Buttons
+ A8 r, ?1 N0 S1 w7 V" ~9 t8 _) Z! e/ Q# L$ L; d
Net "btn" LOC = B8;
4 y. _0 O5 j- c8 |) r% K+ k6 y
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5 z/ Z; G1 L" R2 ~6 Z6 U## Switches
. _' `4 h9 I% Z! M7 y/ h) `: o: H6 O4 t- c+ K1 U
Net "sw<0>" LOC = T10 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L29N_GCLK2, Sch name = SW08 o0 P* Q9 g; u2 o7 O" g

% a! A* F$ Z8 W$ W) NNet "sw<1>" LOC = T9 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L32P_GCLK29, Sch name = SW1, ]$ H/ F( \+ V' w' E8 _
: G1 A" X$ G3 F1 M& K4 }$ Y
Net "sw<2>" LOC = V9 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L32N_GCLK28, Sch name = SW2) `. ]$ b, H9 Q# L+ B" ?$ m2 u8 l

* g4 c7 X6 F- yNet "sw<3>" LOC = M8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L40P, Sch name = SW3* ~! s3 u  u: }3 e+ k

2 G  N# h4 [# I! E" W- BNet "sw<4>" LOC = N8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L40N, Sch name = SW49 U2 M) ~+ x3 G0 h6 ~: @( ~
- L4 @* ~4 q5 N6 C; F
Net "sw<5>" LOC = U8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L41P, Sch name = SW5
7 p0 z) L8 H) X
. }6 Y/ t' N' I% r) {: g9 FNet "sw<6>" LOC = V8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L41N_VREF, Sch name = SW67 B& F! x1 {# X+ v2 O9 o2 U1 C
; {& s+ v1 K6 Z9 D
Net "sw<7>" LOC = T5 | IOSTANDARD = LVCMOS33; #Bank = MISC, pin name = IO_L48N_RDWR_B_VREF_2, Sch name = SW76 U- i/ M/ T* y. H0 P9 G
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## VGA Connector) m2 m, W9 w* I. V9 {
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NET "red<0>" LOC = U7 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L43P, Sch name = RED0
+ D. ?+ ?1 k/ m# B& n! W9 d5 N2 |9 h+ P
NET "red<1>" LOC = V7 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L43N, Sch name = RED1
  b5 [% \  ^7 ]& m  o, V/ K% Z' A5 s/ I5 i4 b
NET "red<2>" LOC = N7 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L44P, Sch name = RED2
- m; g1 _8 g: L0 I% \7 U# C$ e* v. t% B! G$ p! E# F* P" g! t. T
NET "green<0>" LOC = P8 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L44N, Sch name = GRN0
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NET "green<1>" LOC = T6 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L45P, Sch name = GRN1
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NET "green<2>" LOC = V6 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L45N, Sch name = GRN2
; A9 @# L: @( F% O$ v* o7 C/ s3 e0 O! b5 b3 x& ~# h
NET "blue<0>" LOC = R7 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L46P, Sch name = BLU1
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. g+ p  g* o6 q4 I) W; fNET "blue<1>" LOC = T7 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L46N, Sch name = BLU23 d3 Z, o  z" t1 G2 I* ~* n

/ C- E# m: q/ c# F6 t& N5 x1 L. m7 C6 L% W
: d8 n8 L% [4 ^
NET "Hsync" LOC = N6 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L47P, Sch name = HSYNC
% e" ^3 ]; X# {# m8 _5 H# d* r' |, K
NET "Vsync" LOC = P7 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L47N, Sch name = VSYNC
1 v6 Z% S# p8 P, U9 B- _* W2 q; @5 ^$ h2 ~3 F: e: P
## Switches% x1 V7 ^, `. F5 h4 s, g# @
- V2 G5 n& x& H0 T( ]
Net "sw<0>" LOC = T10 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L29N_GCLK2, Sch name = SW0
; d) f2 f( O  G" \) n8 E
& N  J0 u. D' {7 ENet "sw<1>" LOC = T9 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L32P_GCLK29, Sch name = SW1) c0 u- C+ S" l% E& O4 f
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Net "sw<2>" LOC = V9 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L32N_GCLK28, Sch name = SW2
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) C+ s4 p8 }, }7 D7 ENet "sw<3>" LOC = M8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L40P, Sch name = SW3" Z. t( x* n; U
0 T6 ?4 r% E6 y; `) Y
Net "sw<4>" LOC = N8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L40N, Sch name = SW4- a0 P& E: U# I0 M

# O7 |, ~9 `( E6 Y  ]Net "sw<5>" LOC = U8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L41P, Sch name = SW5# @% _! R0 _6 j" T* @
6 M  N! \) M( B6 S9 [
Net "sw<6>" LOC = V8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L41N_VREF, Sch name = SW6
! R) Y- J# f3 e( ~' [# C3 d- b5 z& T3 z. Z4 d" S# u
Net "sw<7>" LOC = T5 | IOSTANDARD = LVCMOS33; #Bank = MISC, pin name = IO_L48N_RDWR_B_VREF_2, Sch name = SW75 H9 T2 K1 \, h/ _/ s; J3 j- F
+ i0 x* Z) X! r5 z: q- d3 o

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以上是程序的全部内容" R& X" ?& O, P
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编译后没有错误  经检验实际结果与预期结果一致
这是源程序所有文件

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relchhiclty · 发表于 2019-4-11 15:49

最近正在找这方面的资料谢谢楼主分享

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在屏幕上显示大写字母DMH的VGA控制器

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