转——【FPGA代码学习】乘法器

Taio · 发表于 2019-4-11 07:00

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转——【FPGA代码学习】乘法器
三位数相乘数学乘法表达式
                                    A1    A2    A3
                              * B1    B2    B3
   -------------------------------------------
   +                         B3A1    B3A2 B3A3
   +             B2A1 B2A2    B2A3
   +  B1A1 B1A2 B1A3
   --------------------------------------------
         5列    4列       3列       2列    1列

串行乘法器：

module multi_CX(clk, x, y, result);
input clk;
input [7:0] x, y;
output [15:0] result;
reg [15:0] result;
parameter s0 = 0, s1 = 1, s2 = 2;
reg [2:0] count = 0;
reg [1:0] state = 0;
reg [15:0] P, T;
reg [7:0] y_reg;
always @(posedge clk) begin
case (state)
s0: begin
count <= 0;
P <= 0;
y_reg <= y;
T <= {{8{1'b0}}, x};
state <= s1;
end
s1: begin
if(count == 3'b111)
state <= s2;
else begin
if(y_reg[0] == 1'b1)
P <= P + T;
else
P <= P;
y_reg <= y_reg >> 1;
T <= T << 1;
count <= count + 1;
state <= s1;
end
end
s2: begin
result <= P;
state <= s0;
end
default: ;
endcase
end
endmodule; T6 E! X& [* Z2 g2 {2 o* H

流水线乘法器

module multi_4bits_pipelining(mul_a, mul_b, clk, rst_n, mul_out);
input [3:0] mul_a, mul_b;
input clk;
input rst_n;
output [7:0] mul_out;
reg [7:0] mul_out;
reg [7:0] stored0;
reg [7:0] stored1;
reg [7:0] stored2;
reg [7:0] stored3;
reg [7:0] add01;
reg [7:0] add23;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
mul_out <= 0;
stored0 <= 0;
stored1 <= 0;
stored2 <= 0;
stored3 <= 0;
add01 <= 0;
add23 <= 0;
end
else begin
stored0 <= mul_b[0]? {4'b0, mul_a} : 8'b0;
stored1 <= mul_b[1]? {3'b0, mul_a, 1'b0} : 8'b0;
stored2 <= mul_b[2]? {2'b0, mul_a, 2'b0} : 8'b0;
stored3 <= mul_b[3]? {1'b0, mul_a, 3'b0} : 8'b0;
add01 <= stored1 + stored0;
add23 <= stored3 + stored2;
mul_out <= add01 + add23;
end
end
endmodule
7 k4 X7 k0 K: X! Q$ [

kinidrily · 发表于 2019-4-11 15:59

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