VHDL流水灯设计

Taio

VHDL流水灯设计

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library ieee; use ieee.std_logic_1164.all; ! J6 U- t3 k/ S5 H1 [) Y5 E3 Z) Ause ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; 1 n/ W3 l, j0 t# t" X1 P/ qentity liushui is port( clk:IN std_logic; 9 r, @* ^% I3 \, y) uclr:IN std_logic; ; Q# ~6 L% s$ s) N8 K* w4 d/ Sena:IN std_logic; - m$ n% h" i# i! a; r# c( g" c$ Y; G5 wyut std_logic_vector (7 downto 0) ); end; architecture behave of liushui is % t7 i! L& N9 d# e$ U# jbegin signal y_out:std_logic_vector(7 downto 0); process(clk,clr,ena) if clr = '0' then y_out<= "00000001"; elsif clk'event and clk = '1' then if ena = '1' then y_out <= y_out<<1; end if; end if;end process; y <= y_out; end behave; . \* h6 i: x- |3 Y+ _: z+ x) G, p

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helendcany

这就去看看可行吗