verilog 基础语法-端口

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verilog 基础语法-端口

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1 模块结构 &nbsp; &nbsp; 端口： module 模块名(端口1, 端口2, 端口3) &nbsp; &nbsp; 内容： * }. @  V# \/ ^7 E* V&nbsp; &nbsp; &nbsp; &nbsp; I/O说明： &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; input 端口名; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; output 端口名; &nbsp; &nbsp; &nbsp; &nbsp; 内部信号： &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; reg [width-1:0]&nbsp; r变量1,r变量2; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; wire [width-1:0] w变量1,w变量2; &nbsp; &nbsp; &nbsp; &nbsp; 功能定义： &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; a. assign 连线 &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; assign a = b&c; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; b. 实例化其他元件 3 n. h9 l! L7 v- D# z&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; and and_inst(q, a, b); &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; c. always模块   Y' \- R* y" I( R&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; always @(posedge clk or posedge clr) &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; begin ( ~* V0 e( }5 k: d- Z&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; if(clr)&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; q <= 0; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; else &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; if(en) &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; q <= d; 0 I2 l3 n% u3 N8 ^; n# V/ T&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; end . ~9 `8 H9 T2 M0 W$ I' F $ f: ~! ?$ R% J7 T. k2 }---------------------

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谢谢楼主的分享