verilog 基础语法-数据类型 常量 变量

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verilog 基础语法-数据类型 常量 变量

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' a5 X$ G0 E6 c8 L1 M&nbsp; &nbsp; 常量： ! A. i. a- L& y' F1 e( k" R&nbsp; &nbsp; &nbsp; &nbsp; 整数：<位宽 num'><进制 b|o|d|h><数字>，例如 4'b1010 &nbsp; &nbsp; &nbsp; &nbsp; x值(不定值)和z值(高阻值，也可用?代替) & Z, b2 q9 y! r" z) T&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; x和z可以标识某一位或者某一个数字 &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; 4'b10x0,4'bx,4'b101z,4'bz,4'b? &nbsp; &nbsp; &nbsp; &nbsp; 负数：整数最前面加- &nbsp; &nbsp; &nbsp; &nbsp; 下划线：分割数字部分，更加易读(8'b1000_1000) &nbsp; &nbsp; 参数：parameter $ ]) U! p/ k% E* K/ @3 O0 B+ s* i&nbsp; &nbsp; &nbsp; &nbsp; parameter 参数名=表达式; , ^$ O1 a. P: m5 d&nbsp; &nbsp; &nbsp; &nbsp; 表达式只能是数字或者定义过的参数 4 {6 l" }$ z  R2 G- P&nbsp; &nbsp; 变量： + D& `- [& u; f, s&nbsp; &nbsp; &nbsp; &nbsp; wire型：wire [n-1:0] 数据名; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; wire表示信号，常用来表示assign关键字指定的组合逻辑信号 ' p9 V- n  L' T6 _8 p. F/ n5 _&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; wire型信号可以用作输入，输出 5 m& ^- ~7 e" f( I% }7 g' M6 N* y&nbsp; &nbsp; &nbsp; &nbsp; reg型：reg [n-1:0] 数据名; 0 q1 z+ G4 f) E: w5 A&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; 对存储单元的抽象 3 [$ W, Q- e! \" p/ C2 _# C" v&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; 常用来表示always模块内的指定信号，常代表触发器 / P/ n9 C1 i9 J; N# k&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; always块内被赋值的每一个信号都必须定义为reg型 * `* o1 d  a4 d8 p: w3 e* x+ D7 w1 Q  W&nbsp; &nbsp; &nbsp; &nbsp; memory型：reg [n-1:0] 存储器名[m-1:0]; 8 {/ ^. E/ ~. z&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; reg [n-1:0]表示基本存储单元的大小 $ p% c+ R% h) K! @4 M  v&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; 存储器名[m-1:0]表示基本存储单元的个数，存储空间的容量 * B2 b% p0 q  b9 `/ t% M% ?/ t&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; 对存储器进行地址索引的表达式必须是常数表达式 &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; 一个n位寄存器可以在一条赋值语句里进行赋值，而一个完整的存储器不行 2 x9 |8 C. O* S# W&nbsp; &nbsp; 运算符及表达式： ! B3 }" d" R$ @: p1 D8 H# K4 j&nbsp; &nbsp; &nbsp; &nbsp; 基本运算符：+ - * / %   r' B% X; m2 s- ?) j&nbsp; &nbsp; &nbsp; &nbsp; 位运算符：~ & | ^ ^~ &nbsp; &nbsp; &nbsp; &nbsp; 逻辑运算符：&& || ! # d$ x$ d$ {( M3 S% `6 G&nbsp; &nbsp; &nbsp; &nbsp; 关系运算符：< > <= >= / u1 ^0 {2 T' x4 r6 H6 D& |&nbsp; &nbsp; &nbsp; &nbsp; 等式运算符：== != (不管x、z，结果可能是不定值) &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; === !==(对参数的x、z都进行比较) &nbsp; &nbsp; &nbsp; &nbsp; 移位运算符：<< >> ( J: j5 q' [7 L&nbsp; &nbsp; &nbsp; &nbsp; 位拼接运算符：{ }，将几个信号拼接起来，例如{a,b[3:0],w,3'b100} &nbsp; &nbsp; &nbsp; &nbsp; 缩减运算符：C =&B;C =|B;C =^B; ' x8 Z( g6 Z+ C+ x( p- ^&nbsp; &nbsp; &nbsp; &nbsp; 优先级别：和c语言差不多，加括号 : w. _. m# A2 o# g7 t  ?' c&nbsp; &nbsp; 赋值语句： &nbsp; &nbsp; &nbsp; &nbsp; 1)非阻塞赋值方式(b <= a) 4 c8 Q7 t1 x( i5 p. j" D&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; a.块结束才完成赋值 &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; b.b的值不是立刻就改变的 , Q1 L8 I$ S; J, w3 W&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; c.在可综合的模块中常用 1 |  C  _" b- ]9 s" o: e&nbsp; &nbsp; &nbsp; &nbsp; 2)阻塞赋值方式(b = a) " Y+ M- L3 X7 H3 d&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; a.赋值语句执行完成后，块才结束 &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; b.b的值在赋值语句执行后立刻改变 + }* o5 A- r8 ~+ {$ `% R&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; c.可能会产生意想不到的结果 &nbsp; &nbsp; &nbsp; &nbsp; 简单理解： &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; 非阻塞赋值用了多个触发器，每次时钟到达，所有触发器都触发一次 &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; 阻塞赋值连到同一个触发器上，时钟到达，导致所有寄存器被赋值 ---------------------

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