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. D4 `/ q3 P: x5 zvsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" flow_led_vlg_tst
& q( a+ H0 |$ _2 B3 }5 ]# vsim -gui "+altera" -l msim_transcript -do "flow_led_run_msim_rtl_verilog.do" $ G- }! n) F# B" U
# Start time: 15:52:59 on Nov 23,2018* T8 W- T7 y; B
# ** Note: (vsim-3812) Design is being optimized...& z2 y$ k- A2 O2 b* R; }, D; |- ~+ n
# 9 R9 j' s; _; [3 H$ L) \( R
# ** Fatal: Internal Error - vopt returned success but vsim could not find a design to simulate!. Please contact customer support for further assistance.! R2 M4 _: ~. w* l
#
( y$ I z7 n( k l# Error loading design
l9 Z$ Q- v4 L3 y0 w+ Q# [# Error: Error loading design, z2 V0 R8 \( L! ?( W' x9 W) y
# Pausing macro execution' x) |, _4 ?8 z0 [$ \
# MACRO ./flow_led_run_msim_rtl_verilog.do PAUSED at line 40 |
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发表于 2019-2-14 14:37
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支持！
反对！