TA的每日心情 | 奋斗 2020-7-22 15:05 |
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签到天数: 3 天 [LV.2]偶尔看看I
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Hyperlnyx中仿真,U1芯片为XCZU11EG-2FFVC1760E,
2 Q- r2 I; }) v- v/ {使用IBIS模型为zynquplus.ibs d- l5 R2 y/ H+ t' x0 S8 \
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[IBIS ver] 5.1
9 a* o$ t/ \: P9 I1 I3 Z' S[File name] zynquplus.ibs
! t2 v# g, |) h+ b2 Y[File Rev] 1.12
' G; \. b/ Q3 k6 U* [( K7 z[Date] 22-MARCH-20183 Z. T% i) U- K {% }6 @, c/ k
[Source] Derived from spice models, rev1.0, using
( D, a1 @: G' X4 z1 ] hspice 2014.09-SP1-2
: g- N5 K1 a0 _0 \* x% G: Y[Notes] Xilinx IBIS file for Zynq UltraScale Plus I/O standards.
6 I3 g6 W: c$ p2 P9 f All models are preliminary.* @* j2 v) i8 I) ?
The version of IBISCHK used is ibischk5 V6.0.1.
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[Disclaimer] The data in this file is derived from SPICE simulations using! F+ q6 x; F9 ^7 K2 E3 v6 ?+ m+ t
modeling information extracted from the target process. While
% d$ p5 y8 u7 g! d a great deal of care has been taken to provide information
; t- s6 H4 |& r0 @ that is accurate, this model is considered preliminary as it
1 U7 a- q( B- | ~7 V has not been verified by actual silicon measurement. Treat the7 `+ Z! P; e& R- d3 Y4 ^
data in this model as preliminary until actual silicon
1 _0 S& l. o. \. ] verification is peRFormed.
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4 L! t5 N8 G+ p) S[Copyright] Copyright 2016, Xilinx Inc., All rights reserved
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仿真的时候报错如图,请问各位朋友这个该怎么解决啊?2 r! U9 Q. T% s& Y8 O3 E4 F) d- g
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