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library ieee;
$ n: T0 e6 x' X- _) iuse ieee.std_logic_1164.all;: F, k' ~1 P* ^4 r
entity d_top is( ?# o7 p5 Z/ t3 J+ O f
port(d,lcr,lck: in std_logic;& n. `* h+ K. ^
q: out std_logic);
4 \( N7 c0 C! s. P3 f* Q/ aend d_top;. K: y9 s1 q8 D2 P6 p; A1 O
architecture dd_top of d_top is
" ~$ N$ @+ @) S# Y/ v |) D9 rbegin. y" r8 O$ e# `1 F4 X
process(lcr,lck): d y( O6 Z O8 T+ D) y
begin& y7 q4 O3 P. ^, {, a. a
if (lcr='0') then
: x! B" ]# b0 q q<='0';
- b! y. v" l) r elseif (lck'event and lck='1') then
( N/ g+ v- N$ H3 M$ T3 v q<=d;0 e3 c @/ c* ^# q5 o5 \: p
end if;
T4 S7 L* H, E end process;
9 v! T! I8 U! E; C* _2 [7 @end dd_top;; e" U, ^! e" J# h
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