新手，求大神指点这段VHDL代码错来哪儿？

624132806

library ieee;
use ieee.std_logic_1164.all;
/ ^2 y& X! i7 [8 u" F' \  }entity d_top is
port(d,lcr,lck: in std_logic;
q: out std_logic);
end d_top;
+ A2 l# c4 H5 C' e) Marchitecture dd_top of d_top is
begin
! Q# J) e& ]0 _2 {& r  process(lcr,lck)
. K0 _9 w7 n; H" ]2 Q  begin
: l5 V+ {3 d5 U( r- W' E    if (lcr='0') then
      q<='0';
    elseif (lck'event and lck='1') then
/ V& I$ Y" R4 v8 ?2 ~& h; r      q<=d;
    end if;
+ q2 K( x' b6 ~$ t6 i  end process;
end dd_top;
, X9 _- A. M. L+ w8 ~