新手，求大神指点这段VHDL代码错来哪儿？

624132806

library ieee;
$ n: T0 e6 x' X- _) iuse ieee.std_logic_1164.all;
entity d_top is
port(d,lcr,lck: in std_logic;
q: out std_logic);
4 \( N7 c0 C! s. P3 f* Q/ aend d_top;
architecture dd_top of d_top is
" ~$ N$ @+ @) S# Y/ v  |) D9 rbegin
  process(lcr,lck)
  begin
    if (lcr='0') then
: x! B" ]# b0 q      q<='0';
- b! y. v" l) r    elseif (lck'event and lck='1') then
( N/ g+ v- N$ H3 M$ T3 v      q<=d;
    end if;
  T4 S7 L* H, E  end process;
9 v! T! I8 U! E; C* _2 [7 @end dd_top;