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不方便截图,这是新找到的,是17.2的问题0 A& H7 K5 |; \7 r9 ~8 t
" v( W# V3 p" \6 l+ s) w0 n1.Close the design if it is open in Allegro PCB Editor.
# U- |* {+ H3 o, N7 H* _2.Add the CDS_XNET_STATE_UI variable with a value of 1 to the User variables section in the Environment Variables form.) W4 r6 [8 \1 u! y, A
3.Open the design in Allegro PCB Editor.
# l4 d- ^- _ z3 _$ j4.Go to File > Import > Logic and, if not already set, set the Import Logic Type to Design Entry HDL.
& W4 F2 V) h7 n" Q5.Open Constraint Manager.
9 [# j+ y- p. B% b3 |6.Select Tools > Options.
0 z+ \- [0 L3 F7.Select the Create XNets and Differential Pairs using DML Models (same as SPB 16.6) option. |
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