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不方便截图,这是新找到的,是17.2的问题
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1.Close the design if it is open in Allegro PCB Editor.
- `1 v) A4 @" O4 j0 ^9 W# b3 ~2.Add the CDS_XNET_STATE_UI variable with a value of 1 to the User variables section in the Environment Variables form.9 j. v4 p' N3 Z: g1 ^. `# J$ S
3.Open the design in Allegro PCB Editor.
0 Z( t, O7 A# x) u, d/ x4.Go to File > Import > Logic and, if not already set, set the Import Logic Type to Design Entry HDL.; Y; U( ~3 I( f
5.Open Constraint Manager.
( e# j' O( H( |( J* R2 j6.Select Tools > Options.
3 g% n' G5 G c9 n0 j d- v7.Select the Create XNets and Differential Pairs using DML Models (same as SPB 16.6) option. |
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