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不方便截图,这是新找到的,是17.2的问题
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$ p9 [$ e3 I: ~0 C5 b4 W. E, S1.Close the design if it is open in Allegro PCB Editor.- F+ j: ]9 x& \, ]) P- k
2.Add the CDS_XNET_STATE_UI variable with a value of 1 to the User variables section in the Environment Variables form.
7 k) f, {8 V3 J l1 s" k4 c3.Open the design in Allegro PCB Editor.( N& L$ W( I. J3 L T
4.Go to File > Import > Logic and, if not already set, set the Import Logic Type to Design Entry HDL.: g: p, [# K& [& P
5.Open Constraint Manager.
2 b! J3 U" T0 P% k" e% `1 X0 p6.Select Tools > Options.
/ _+ R! W$ c" v0 k5 _0 ]+ |. M8 D7.Select the Create XNets and Differential Pairs using DML Models (same as SPB 16.6) option. |
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