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不方便截图,这是新找到的,是17.2的问题/ S3 J: A5 o% X o' @ D }
, c# [& e2 O2 P% F1.Close the design if it is open in Allegro PCB Editor./ H, U$ C/ _- \$ X
2.Add the CDS_XNET_STATE_UI variable with a value of 1 to the User variables section in the Environment Variables form.3 H& A- Z- g: H. Z$ z/ `0 R
3.Open the design in Allegro PCB Editor.
+ ?) O7 g9 Q$ X# X% i4.Go to File > Import > Logic and, if not already set, set the Import Logic Type to Design Entry HDL.% h# P' ]- w# G
5.Open Constraint Manager.2 ~+ N! @+ u0 I) N( ~
6.Select Tools > Options.
& r! t' T) ]+ [, `6 m# r7.Select the Create XNets and Differential Pairs using DML Models (same as SPB 16.6) option. |
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