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高速数字信号设计和高速互连( L9 p5 z$ _$ P9 V- e# h# H8 c6 o
CHAPTER 1 Transmission Line Fundamentals.......................................... 1: C9 j* w: O) y, N/ }( e1 t" \0 o1 ]& G
Basic Electromagnetics.................................................................... 1
6 E+ b- p+ u+ `9 ]- C1 a6 v0 i8 kElectromagnetics Field Theory................................................... 1' j# A9 c) _7 K- c$ ~, a: c( c
Propagation of Plane Waves....................................................... 6
7 |2 k( f, H+ i# ~) H) ?Transmission Line Theory............................................................. 10/ S9 S7 t0 i; V
Wave Equations on Lossless Transmission Lines.................... 11
6 u. |+ O: K5 H2 g$ N: `* wImpedance, Reflection Coefficient, and Power Flow5 d! V5 y" h& w
on a Lossless Transmission Line......................................... 14
- C ~+ _ U4 I* iTraveling and Standing Waves on a Transmission Line ......... 16! B8 |: O# S$ j; z8 c: z5 A
Transmission Line Structures ........................................................ 184 r: e" |9 A, t* ~" j
Stripline ..................................................................................... 19
$ V$ E6 y! I8 [6 t% t5 vMicrostrip.................................................................................. 20
3 U# F- j( q- d# c0 D2 F7 dCoplanar Waveguides ............................................................... 21
+ d! b! ?9 g" W. [+ l! M7 ^# O* x' lNovel Transmission Lines ........................................................ 22
, V+ q* l A% u. P1 x& `References ...................................................................................... 26
, z5 y- S* g, s- c, CCHAPTER 2 PCB design for Signal Integrity........................................... 27
E6 g5 O) c6 L rDifferential Signaling..................................................................... 27
& v) W9 | D% f2 ~- X) m; GImpedance ................................................................................. 28
6 a3 I$ N0 r7 `Time Domain Analysis .................................................................. 31
' w5 z, p/ e' ?0 C% }Eye Diagram ............................................................................. 31
7 u. _7 K: M) p/ A! w. u- x; FJitter........................................................................................... 33: S, o6 x2 n3 B' E4 E: {- ?2 ?
Frequency Domain Analysis.......................................................... 42
7 n& L6 k! I9 m. GSpectral Content........................................................................ 42! A4 h! b- M3 V, J% p* f3 v
Insertion Loss............................................................................ 44, }- K3 C+ q" u7 j
Integrated Insertion Loss Noise................................................ 46- V9 l0 W1 D o, ~- a6 U$ @
Return Loss ............................................................................... 49
; O3 ^2 m7 V: `! \1 U; ^Crosstalk.................................................................................... 51
, a. p" s$ P) tIntegrated Crosstalk .................................................................. 54; h3 D) w6 c0 g4 }, _+ x; ]4 e
Signal-to-Noise Ratio................................................................ 55: Q4 k5 U' I; S! a
Stack-Up Design ............................................................................ 582 _$ o; B8 c# j3 G7 ^3 y' U
Impedance Target (Routing Impedance) .................................. 59$ U2 V/ n7 T0 u( B! f+ d+ L! i
PCB Losses ............................................................................... 61" N- ?( Q2 d$ f5 A, m! i
Dielectric Loss .......................................................................... 62
$ \1 K" P, I& Y& e2 b: R/ f; WConductor Loss ......................................................................... 651 @) U/ {9 e; I6 d! V" b
Crosstalk Mitigation through StackUp..................................... 68
7 q/ w1 H2 c( F4 H4 x. TDual Stripline ............................................................................ 73+ Z; u( z' B# g; N, \/ _
v, s b) v# ^2 O8 ~) c
Densely Broadside Coupled Dual Stripline.............................. 84% o- I5 L9 v' ]& P* Y0 a
Via Stub Mitigation .................................................................. 86. @4 Y! `1 [8 z4 o7 T# g: `' Y, K# {! n
PCB Layout Optimization ............................................................. 95, G' r+ }2 m o! E
Length Matching....................................................................... 96. O6 u: t" R B- v$ l. O7 r( P- o
Fiber Weave Effect ................................................................... 99
, M6 @! {- x t* S6 j$ }+ @Crosstalk Reduction ................................................................ 101
( u- N% E+ [! P+ iNon-Ideal Return Path ............................................................ 107
2 Q- Y( e3 C8 x# Z: gPower Integrity........................................................................ 110
7 z# f5 y2 }9 V2 J" Y7 ?Repeaters ................................................................................. 111
& I) l, G0 E: V' {References .................................................................................... 115
! e5 r @- W! d. }$ }CHAPTER 3 Channel Modeling and Simulation.................................... 117
4 |& o# i+ T* P. U1 v2 j5 ?Transmission Lines ...................................................................... 117
; P7 W6 ^9 g. T3 D+ XCausality.................................................................................. 117& X/ c( f) M, N" d( y0 g' [
Checking for Model Causality................................................ 118( Q4 A) w) s3 i4 u( T# _! y
Causal Frequency-Dependent Model...................................... 120
4 R, L3 C, o, s2 fCopper SuRFace Roughness..................................................... 121
; y- L, s5 y: B: z8 AConductivity............................................................................ 1265 ^8 ?7 q# \/ i2 `$ K2 l+ _
Environmental Impact............................................................. 127
5 `9 z5 V t* K* R* m$ pModel Geometries................................................................... 130" r) U1 D. E( T2 I% o; w3 d
Corner Models......................................................................... 133
0 \; [6 z0 D# b% j3 xIdeal Assumptions: Homogeneous Impedance....................... 137
; h, @/ B3 @4 n$ eIdeal Assumptions: Crosstalk Aggressors .............................. 137' o' _$ e. S1 H# s" L
Transmitters.................................................................................. 138+ ` E: z' n. o
IBIS Models ............................................................................ 138
+ K2 h: q" q. S% v* a; O( v, ^' MSpice Voltage Source Model .................................................. 139
, W/ W- |# }+ h* L6 d' f3D Modeling ................................................................................ 141' W$ h. c0 ]2 _2 W% `
Ports/Terminals ....................................................................... 142 e n+ X; [6 v: W2 J6 H5 l: U9 s
Model Analysis Settings ......................................................... 144
8 O5 c1 }$ m4 n) vPlated-Through-Hole Via............................................................. 146: ^0 d8 p p* n! @5 u4 Q) H* \
Model Techniques................................................................... 147
O0 e- V8 _" h0 L1 i- _( v. IPre-Layout Approximation ..................................................... 148! G4 z5 G6 `+ h6 b, N
Pre-Layout Modeling .............................................................. 148
5 q- ?, G3 u% |, Q' i, R p2 VPost-Layout ............................................................................. 1490 }! b X0 c* o! k0 a7 a. B
Connectors.................................................................................... 150
) M' T" |0 z3 k1 \4 ?Connector Variability.............................................................. 150
4 `, `. L( F7 T5 [: y5 ]Signal Selection....................................................................... 150
7 }4 J5 ^# r; TSeparated Via Models............................................................. 152
* e) f0 B0 K. F+ m9 `: E! T+ a+ KUnconnected Pins.................................................................... 153
a3 @) ]3 e! `% ~& ePhysical Features..................................................................... 1549 n- D0 t6 u) ?. B
Design Optimization ............................................................... 154
/ ?0 }2 E: G \# L5 z: b5 `" y; WPackages....................................................................................... 1566 U4 A( f. y- P
C4 Escape................................................................................ 1584 ~" ^$ M, H* d" i5 w+ I
vi Contents
7 s4 Y# j& f/ ]$ \4 Y$ p4 u9 m. xTransmission Line................................................................... 1586 e% n% Z. w, M, K; H2 f
PTH Via .................................................................................. 160
1 |8 T! u1 L& T" n7 E. bBGA Model............................................................................. 160
' b8 Y, x$ j6 t( zSignal Selection for 3D Package Structures........................... 161+ ]# d% w. m* E5 ]/ z
References ....................................................................................161! D( u# y% B1 d8 I
CHAPTER 4 Link Circuits and Architecture .......................................... 163 t% n6 a9 l. [ Q
Types of Link Circuit Architectures............................................163# o9 T0 I8 Y' s1 e; W9 A
Embedded Clock Architecture................................................ 1636 h: g) O! O, k
Forwarded Clock Architecture................................................ 164+ N' U+ X' Z+ Z3 Z2 g
Termination ..................................................................................165
3 Y: f% \/ C2 x: l) C5 P& P0 jDC and AC Coupling.............................................................. 1657 l, N# m) S I/ {% i1 p5 }. p
Termination Type.................................................................... 166
! f; p# m! i) tTermination Circuits ............................................................... 167
, ~/ k4 F& @2 CTermination Calibration Circuits............................................ 168
: k1 v: @) I' ?$ I" H, [( wTermination Detection Circuits .............................................. 169% z; K: q) f/ q/ @7 @6 {$ t! r. W
Transmitter ...................................................................................170
W& Q2 }# |) @Transmitter Equalization......................................................... 1710 [, [* C) ]" n" d4 g+ x+ C( Z9 J- |
Transmitter Data Path ............................................................. 1738 q, i' I5 R. S/ I/ N
Current-Mode Driver .............................................................. 174. V( `$ N% r% B
Voltage-Mode Driver.............................................................. 177
; g! Y% q6 t) k1 ^3 C8 w3 |. [/ zReceiver........................................................................................179$ q* M E* Z) o; _0 w2 q
Receiver Equalization ............................................................. 180
: a- h- X ?) O- F' o$ e3 QReceiver Data Path.................................................................. 182
/ `( l' I' n$ `7 K' w) g2 rContinuous-Time Linear Equalizer ........................................ 184# @6 `$ @$ f) u5 p- |/ c0 b V" K
Decision Feedback Equalizer.................................................. 184
7 m7 t9 g! w8 k% B8 uData Sampler........................................................................... 1862 U" L; Z; m/ Y; f
Error Sampler.......................................................................... 186
6 `7 f: n1 D5 x, i. ]Receiver Calibration ............................................................... 187/ v+ X2 a! V' n/ w |, s
Receiver Adaptation................................................................ 188
2 H( d- Y, q. uClock and Data Recovery............................................................190+ d4 D! ` N7 F+ {3 p2 Z
Clock and Data Recovery Loop ............................................. 191# `- U8 `* ` b$ L: O6 B6 q0 [# M
Phase Detectors....................................................................... 192
5 n% @$ P3 N: Z0 `Forwarded Clock Receiver ..........................................................195
4 d* a7 E" t3 B$ PDelay-Locked Loop ................................................................ 195
2 ?+ F# f, a7 bDesign for Test/Manufacture.......................................................195! Z; D4 b5 E6 S% X8 d& V5 w
Analog DFx Features .............................................................. 196
. ]) \* x Z- j5 y7 ^Digital DFx Features............................................................... 196) S6 `7 j% J) w0 U7 Y7 F. M
References ....................................................................................198 ^# ? @9 A8 F% b, K, s: C
CHAPTER 5 Measurement and Data Acquisition Techniques............... 199
+ P- V8 L: D3 w- tDigital Oscilloscope Measurement..............................................1996 [' h, |! Z7 M
Real-Time and Equivalent-Time Sampling Scopes ............... 1991 L. l* P5 t( N& j1 ~; f
Contents vii
( j: t, ?% M5 W+ t/ Y- Q O: WBandwidth ............................................................................... 200
. r* X! V. ~2 V' w8 `Scope Digital Filter Applications ........................................... 2022 c% |% G8 `! X# m- |' E, M
TDR Measurements ..................................................................... 204
% b% r; i0 w i- e# g4 O% B6 P% aDe-skew Differential Pairs with TDR .................................... 205
* W C$ q( T- o3 MChannel Characterization with TDR ...................................... 207# J# D* d9 W7 p9 m0 m
Return Loss Measurement with TDR..................................... 209
6 a1 J9 W* g, sVector Network Analyzer Measurement..................................... 211
X" w: D A2 u1 Z- KWhat is VNA?......................................................................... 211+ `, w! ^- U# p0 S* ~3 J
VNA Error Sources and Calibration....................................... 213& u8 @+ @! I) ~6 q6 H, B: Y
Full Two-Port SOLT Calibration Procedure .......................... 217
4 u$ j3 W" r! jExample of Measurement Using VNA................................... 217
& m5 c! e E6 A o4 e! LVNA Measurement Procedure................................................ 218) H0 z" j% N( V8 _+ ~' j1 `8 K
References .................................................................................... 219
7 e4 F: ?* b, ~0 oCHAPTER 6 Designing and Validating with Intel Processors............... 221
2 ~* {! ^3 Z) H3 K- \# KDesigning Systems with Intel Devices........................................ 2217 ?& A& L1 s0 D$ b: W' I& y
Interconnect Model ................................................................. 221! i5 ^% k# o4 u) U6 `
Equalization Models ............................................................... 223
& p- K7 u! J! a* a HAutomatic Equalization Adaptation ....................................... 225
' X' O+ r. l" v& v4 k3 O/ }8 j# MPerformance Analysis ............................................................. 227
; g+ g \- } |/ I: k' DSolution from Design of Experiments.................................... 2326 u9 E. T6 W" ]: ]/ \4 `
Solution from Typical Models................................................ 234( p2 e: T1 Y& ~
System Validation with Intel Devices ......................................... 237# P4 U* @( ^, I+ j! z6 _( |
Power-on Preparations ............................................................ 237
0 f% R3 B; }3 ]9 ^4 r( D7 {3 t NTypes of I/O Design Validation ............................................. 238% _1 W( r- n: b" h; r2 V+ @
System Margining Validation Overview................................ 2391 u" T1 X2 l5 Q" ] D; }
DDR System Margining Validation ....................................... 244
' O( }& w8 x K4 \: E! [4 d! t% X: ^High-Speed Serial I/O Margining Validation ........................ 246
/ G; N$ M# E4 m! ^3 rLow-Margin Debug Guidance ................................................ 2495 p- I, s, n7 d" o' I
Summary ...................................................................................... 250& A7 i( B% k9 S: l3 R
References .................................................................................... 250: I' Y- x* ^0 R
Index .............................................................................................................
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