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Fixed CCRs: SPB 17.2 HF021/ t" U$ h) }/ s
06-3-2017
$ G+ `3 F( V& ^: i) y3 e* t========================================================================================================================================================; u6 o2 B4 | a' ^2 E
CCRID Product ProductLevel2 Title
; ]7 ~& W! `# z3 p" `========================================================================================================================================================
4 }( o. J- N x& b2 Q, |1401318 ADW DBEDITOR Bulk Edit - Previously modified cells do not turn blue when selected
K1 O' y4 q! C, J2 w2 T1621446 ADW DBEDITOR Bulk Edit - sorting highlights incorrect cells to mark them as changed* Q3 O1 F- b c/ F0 l- N7 _. A
1743997 ADW LIB_FLOW Match file for standard models is incorrect
5 ]& z' n. N: I" y1746052 ALLEGRO_EDITOR DATABASE PCB Editor crashes when applying no drc property. ~7 Z$ U! ^% k6 v7 W
1736067 ALLEGRO_EDITOR DRC_CONSTR Interlayer checks not reporting DRCs between cline and mask layer
# J* ~* ~6 H( H- o1738587 ALLEGRO_EDITOR EDIT_ETCH Line width changing on slide for ETCH - Conductor (Not on a NET), H2 h! |; j( Z" c0 T/ a
1745277 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes on using the slide command
, j: {" ], ~. a$ e3 j. H3 i# n1747942 ALLEGRO_EDITOR EXTRACT Fabmaster Out does not export arc in pad_shape
9 E* q. U* l7 \) N1737202 ALLEGRO_EDITOR GRAPHICS Setting the variable display_raster_ops; z0 |; h% |& X3 n1 h# |4 q% w2 }
1744042 ALLEGRO_EDITOR GRAPHICS Unused pad suppression is not working on few nets! m* s1 K+ W# C% ~$ X* Q
1703848 ALLEGRO_EDITOR INTERFACES IPC 2581 fails with error 'E- (SPMHGE-268)' and the log file is empty
) k B3 r" v f' T* T1743899 ALLEGRO_EDITOR MANUFACT Glossing dangling vias crashes PCB Editor- W7 ?, E S" ]( q" D* P1 a/ G
1744467 ALLEGRO_EDITOR OTHER The 'logical_op_new' variable is not displayed in User Preferences Editor5 ~2 Y9 z& a9 S. f7 D1 o5 t
1748520 ALLEGRO_EDITOR OTHER TDP fails to load on an empty database
6 O' ?# A! d5 p' F' ?& U4 @2 n1748581 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor crashes when changing default pad geometry$ E( m* x+ d- j' ~ R
1751469 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor crashes/freezes when browsing for a shape symbol; ~/ P& [0 e. `) n
1725948 ALLEGRO_EDITOR SHAPE Shape differences after conversion from release 16.6 to release 17.2-2016/ |9 r, z$ I, n/ `/ p e: X0 S
1729306 ALLEGRO_EDITOR SHAPE Seting shape_rki_autoclip variable causes no void to be generated
( g0 e: D5 O2 C/ T+ U1698876 ALLEGRO_EDITOR UI_GENERAL Tabs are large and text is compressed in release 17.2-2016. \* a. z# r+ ]. M2 m
1698883 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, enlarging icons makes selection boxes/text unreadable on 4K monitors, f) n. G) I& `3 ?
1707933 ALLEGRO_EDITOR UI_GENERAL axlUIMenuFind not locating menu as per x_location
5 Q! }- K O8 k4 p( l! E- _1741460 ALLEGRO_EDITOR UI_GENERAL Right-click, context menu options grayed in some cases after choosing Edit - Copy
; A1 K4 x: b2 M+ p9 ~) s1747588 ALLEGRO_EDITOR UI_GENERAL Interacting with PCB Editor by sending messages is not working+ U' X: r" w7 |1 h0 z8 f
1747488 APD EDIT_ETCH Route connect is improperly affecting existing routes in locked high speed via structures
o( g9 u! D6 Y& g* Z1750182 APD STREAM_IF The stream out settings are not saved
9 L5 F( _ D9 u" V# E. s1752067 ASI_SI GUI Links to differential waveforms do not work in Sigrity SI report
% s& @. z# v Z# |9 R1752131 CONCEPT_HDL COMP_BROWSER Symbol view in part manager doesn't match the symbol version& t k6 {* H! n
1754116 CONCEPT_HDL COMP_BROWSER Default Symbol selected is n°2 instead of n°1 in component Browser
# d$ C+ ~4 i( ?# R$ H/ L0 J1754949 CONCEPT_HDL COMP_BROWSER Part Information Manager displays preview window with the wrong symbol and missing footprint6 ^) l$ R: ]- y0 Y1 K
1721334 CONCEPT_HDL CORE dsreportgen not able to resolve gated part on schematic
7 R, X& \" @4 N3 U7 D1750916 CONCEPT_HDL CORE DE-HDL crashes when trying to uprev a project in release 17.2-2016% m% q1 @1 M# T# H: ?
1711487 CONCEPT_HDL INFRA Restrict opening of release 16.6 designs from a release 17.2-2016 design using File - View Design
3 X$ e" w4 V' g9 b7 @) q. q1746915 CONSTRAINT_MGR CONCEPT_HDL Unable to copy a Physical and Spacing CSet generated from the Constraint Automation flow7 g" m. B6 }2 R$ d
1743523 CONSTRAINT_MGR DATABASE Suppress warning pop-ups from the constraint automation script
- r6 Q0 M7 J6 c( _1 w/ }. B, K1746941 CONSTRAINT_MGR UI_FORMS 'Go to Source' from DRC tab is not working in release 17.2-2016- z p3 S* e+ b
1753010 ECW METRICS Metrics not getting collected due to old license in use
% w8 k4 G, S3 ]( h& R2 k1713052 FSP GUI Pin/Port Name and Group Name are not aligned properly in FPGA Port and Use Pin Mapping for DeviceInstance" K; `/ `/ J( j
1719099 FSP GUI Net naming wrong after building block
: @( L% [7 w0 n1719105 FSP GUI Tabular sorting not working in FPGA System Planner' o' F! `& L) [# A! W1 o {
1720479 PSPICE ENVIRONMENT Probe window does not open consistently on Windows 10 systems- Q( ] a9 B0 Z) Z! H3 o# ?3 m
1723411 PSPICE ENVIRONMENT Probe window does not open consistently on Windows 10 systems
( B; w( N, f: z! l0 D. A9 F( }- [1746628 PSPICE ENVIRONMENT PSpice Simulation Manager displays same message for all simulations in release 17.2-2016, Hotfix 016
% n" E# ~% k+ \# s4 h( Z1745976 SIG_INTEGRITY GEOMETRY_EXTR Arcs with coplanar waveguides are extracted with incorrect spacing! d) _- [4 ?6 a: n. }9 L4 E
1690820 SIP_LAYOUT PLATING_BAR Cannot add fillets to pads with plating bars in release 17.2-2016
' l0 a3 t; l& Y% M& u2 ~* o B# g4 g1725042 SIP_LAYOUT PLATING_BAR Creating a plating bar removes dynamic fillets9 B6 D9 X. l% A7 G4 F" {
1747534 SIP_LAYOUT SHAPE Moving fiducial crashes SiP Layout. Y& w) O% e, R! X' j5 ?6 r6 R* k
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发表于 2017-7-2 18:37
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发表于 2019-2-27 16:42