|
|
Fixed CCRs: SPB 17.2 HF021
, D" \) b# Z; M06-3-2017( x, X1 i, O/ L+ l6 G7 G/ e
========================================================================================================================================================
: v, x4 x6 M p t' q+ ~% X$ hCCRID Product ProductLevel2 Title* Q* z# @) }4 [
========================================================================================================================================================
/ p7 j/ j7 i `9 L' f3 b1401318 ADW DBEDITOR Bulk Edit - Previously modified cells do not turn blue when selected# d+ e& O6 o9 ^5 i* k) c: ^
1621446 ADW DBEDITOR Bulk Edit - sorting highlights incorrect cells to mark them as changed
$ z; V3 n# q# b# Q1743997 ADW LIB_FLOW Match file for standard models is incorrect) z3 X! n' c! e3 Y( v* e
1746052 ALLEGRO_EDITOR DATABASE PCB Editor crashes when applying no drc property
! N5 Q9 G, k0 T: [/ Y1736067 ALLEGRO_EDITOR DRC_CONSTR Interlayer checks not reporting DRCs between cline and mask layer
8 o4 [$ X h* A3 [* n+ U7 ?1738587 ALLEGRO_EDITOR EDIT_ETCH Line width changing on slide for ETCH - Conductor (Not on a NET)
; J6 Q t$ J! C' P! Q0 o; g! \3 f1745277 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes on using the slide command, v" d: n1 M' b o5 j& v' W4 |
1747942 ALLEGRO_EDITOR EXTRACT Fabmaster Out does not export arc in pad_shape
- }2 z% O6 I' B* G `) w% G$ Y0 [1737202 ALLEGRO_EDITOR GRAPHICS Setting the variable display_raster_ops) E2 m7 v. C1 i8 S7 X$ t0 v
1744042 ALLEGRO_EDITOR GRAPHICS Unused pad suppression is not working on few nets9 A+ U, r; N% b
1703848 ALLEGRO_EDITOR INTERFACES IPC 2581 fails with error 'E- (SPMHGE-268)' and the log file is empty. y* A9 C ^2 @- m1 S
1743899 ALLEGRO_EDITOR MANUFACT Glossing dangling vias crashes PCB Editor! n0 R9 o: n- C" m% K2 k2 G6 ~" W
1744467 ALLEGRO_EDITOR OTHER The 'logical_op_new' variable is not displayed in User Preferences Editor9 X, t9 g( W( J$ \! Q# R
1748520 ALLEGRO_EDITOR OTHER TDP fails to load on an empty database
! P: s- @* j/ Z8 o0 H6 Q1748581 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor crashes when changing default pad geometry
G# H$ l0 F& i- g) Z1751469 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor crashes/freezes when browsing for a shape symbol
* O6 D) V M2 N# }: ], E- Z1725948 ALLEGRO_EDITOR SHAPE Shape differences after conversion from release 16.6 to release 17.2-20161 [% D/ p( n" P$ I* s" W, x
1729306 ALLEGRO_EDITOR SHAPE Seting shape_rki_autoclip variable causes no void to be generated# C+ V: _# w9 L, \8 ~8 q* H
1698876 ALLEGRO_EDITOR UI_GENERAL Tabs are large and text is compressed in release 17.2-20167 G/ A4 e6 V! G; m1 S1 @
1698883 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, enlarging icons makes selection boxes/text unreadable on 4K monitors5 W( N H3 e. u. s$ }, z# o# s
1707933 ALLEGRO_EDITOR UI_GENERAL axlUIMenuFind not locating menu as per x_location) Q+ Y1 z& J) j. ^' k
1741460 ALLEGRO_EDITOR UI_GENERAL Right-click, context menu options grayed in some cases after choosing Edit - Copy
3 w( v+ h- L1 v4 ?0 u6 V% l1747588 ALLEGRO_EDITOR UI_GENERAL Interacting with PCB Editor by sending messages is not working
7 y% D! T& o! Y4 }# e1747488 APD EDIT_ETCH Route connect is improperly affecting existing routes in locked high speed via structures5 n( e, T# n$ h
1750182 APD STREAM_IF The stream out settings are not saved
% D* ~, s$ j4 h. d1752067 ASI_SI GUI Links to differential waveforms do not work in Sigrity SI report. n; ?: c0 ~/ s
1752131 CONCEPT_HDL COMP_BROWSER Symbol view in part manager doesn't match the symbol version' j% @ k) q. k- F! [
1754116 CONCEPT_HDL COMP_BROWSER Default Symbol selected is n°2 instead of n°1 in component Browser! r' \) i/ e+ E9 w: p
1754949 CONCEPT_HDL COMP_BROWSER Part Information Manager displays preview window with the wrong symbol and missing footprint
$ b$ X: g9 J' n1721334 CONCEPT_HDL CORE dsreportgen not able to resolve gated part on schematic
; t) i; K. j3 a5 p: ]1750916 CONCEPT_HDL CORE DE-HDL crashes when trying to uprev a project in release 17.2-2016
& Q/ m @) ?; e( I! w# S- k1711487 CONCEPT_HDL INFRA Restrict opening of release 16.6 designs from a release 17.2-2016 design using File - View Design
) \. r3 G. ]* [4 @1746915 CONSTRAINT_MGR CONCEPT_HDL Unable to copy a Physical and Spacing CSet generated from the Constraint Automation flow m2 ^' I7 p$ f E7 h1 `
1743523 CONSTRAINT_MGR DATABASE Suppress warning pop-ups from the constraint automation script
/ F9 q$ F% u2 q& b; ]4 @1746941 CONSTRAINT_MGR UI_FORMS 'Go to Source' from DRC tab is not working in release 17.2-20165 U3 B7 ^8 B; K `: b% o w
1753010 ECW METRICS Metrics not getting collected due to old license in use
' i( D" }. A, o* _1713052 FSP GUI Pin/Port Name and Group Name are not aligned properly in FPGA Port and Use Pin Mapping for DeviceInstance' U0 ~* C, X% z3 V$ c( b
1719099 FSP GUI Net naming wrong after building block
% [; j0 N; Q+ x0 R: t$ |+ @- }, c1719105 FSP GUI Tabular sorting not working in FPGA System Planner
$ f3 B/ \ t1 {4 s7 f2 j1720479 PSPICE ENVIRONMENT Probe window does not open consistently on Windows 10 systems
* D: ~! V6 N. Q ?- B4 B f1723411 PSPICE ENVIRONMENT Probe window does not open consistently on Windows 10 systems
% C' W" s. y, D0 [& T1746628 PSPICE ENVIRONMENT PSpice Simulation Manager displays same message for all simulations in release 17.2-2016, Hotfix 016
; o3 s; _- e f& u3 D+ }. H1745976 SIG_INTEGRITY GEOMETRY_EXTR Arcs with coplanar waveguides are extracted with incorrect spacing7 }' J1 T2 S; I1 G* A
1690820 SIP_LAYOUT PLATING_BAR Cannot add fillets to pads with plating bars in release 17.2-2016
' z( y1 S5 |2 R; D# V1725042 SIP_LAYOUT PLATING_BAR Creating a plating bar removes dynamic fillets
+ z: |$ i ?0 x2 O+ I1 {1747534 SIP_LAYOUT SHAPE Moving fiducial crashes SiP Layout
/ m( Y' G1 T# ]: [3 c |
|
/1 
发表于 2017-7-2 18:37
收藏
淘帖
支持！
反对！
楼主
发表于 2019-2-27 16:42