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Fixed CCRs: SPB 17.2 HF022$ _$ d, n$ _' s& V; M# x
06-16-2017$ F* o; C# E* }; r7 N2 a4 K
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CCRID Product ProductLevel2 Title! y# ^5 L( }7 l R } Y8 F u
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! G! s% k; |7 ?' c8 h1755789 ADW DBEDITOR Checking in HSS Block returns 'Failed to create archive'" G* q* K) y( L/ l5 |/ w# k
1731459 ADW FLOW_MGR Cannot open LRM from Flow Manager
* {. j2 x6 {$ ]9 @1731460 ADW FLOW_MGR Cannot open LRM from Flow Manager
& G2 ^. K& T, W1744081 ADW FLOW_MGR Error regarding configuration file when trying to open Workflow Manager
& S( x) O6 r5 h1756727 ADW LIBIMPORT EDM Library Import fails with java exceptions when merging classifications6 N) d' | _6 W9 j* d8 r
1743763 ADW SRM Find filter is grayed out when Allegro PCB Editor is opened from EDM Flow Manager
! E9 H4 S" J1 `" a1748399 ALLEGRO_EDITOR DATABASE In release 17.2-2016, end caps not visible for certain clines in PCB Editor
( Y2 X: R% f- I: ^0 ?$ Y/ u+ C# d1748522 ALLEGRO_EDITOR INTERACTIV A component mirrored using the 'funckey' command jumps to (0,0) position when the 'move' command is used on it
: O* r( U: T2 H/ c7 w1734983 ALLEGRO_EDITOR INTERFACES Secondary step model does not stay mapped after drawing is reopened
" Q; c' p% t5 s) b. F1753704 ALLEGRO_EDITOR REFRESH Refreshing symbols crashes PCB Editor' H+ J* Y N& N
1493721 ALLEGRO_EDITOR SHAPE Voids on negative planes are not adhering to constraints% M v! j0 S, t
1711242 ALLEGRO_EDITOR SHAPE Route keep out leads to partly unfilled shapes with gaps
2 H* a7 e: M0 m5 d( V8 U' q5 l1726865 ALLEGRO_EDITOR UI_GENERAL Pop-up Mirror command does not mirror at cursor position
+ ^4 d7 ]5 m" t& {' {/ j$ X" P+ c1752987 ALLEGRO_EDITOR UI_GENERAL axlUIViewFileCreate zoom to xy location not working while in user created form.
; P( \- L7 x; T! ?/ Y& U0 x F1755638 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, zoom operations using mouse button not working when axlShellPost() is run8 r4 R/ u) j; h. d! D) x& `" l
1719792 ALLEGRO_PROD_TOOLB CORE Productivity Toolbox Z-DRC hangs or crashes PCB Editor
8 Q: m$ N; `2 d) @) D9 Z1624869 ALTM_TRANSLATOR CAPTURE A structure file is required to translate a third-party schematic to OrCAD Capture
8 _. H" p2 }1 \* r1707416 ALTM_TRANSLATOR CAPTURE Missing components and pins in the OrCAD Capture schematic translated from a third-party tool( Y7 I+ G- B' i4 b8 Y
1708825 ALTM_TRANSLATOR CAPTURE The third-party translator fails to translate the schematic
9 v7 J) u- l% ~7 {* o4 o, P: u/ P1719200 ALTM_TRANSLATOR CAPTURE The third-party translator fails to translate all the pages of a schematic$ N; I( y" E. r9 `0 q
1546070 ALTM_TRANSLATOR CORE Third-party to DE-HDL schematic translation fails, v7 \2 o# m: k0 |6 _! k
1700508 ALTM_TRANSLATOR CORE Third-party PCB translator does not work in release 17.2-2016- V, X8 B. _8 Q) T# h9 k' Q
1699340 ALTM_TRANSLATOR DE_HDL Unable to import third-party schematic into DE-HDL using Import menu in PCB Editor+ Y2 C" q% _) @+ z
1630379 ALTM_TRANSLATOR PCB_EDITOR Third-party translator is not importing clines and vias
/ M1 G4 P8 b! `! q" A' _! ^/ X+ x1708615 ALTM_TRANSLATOR PCB_EDITOR All items of third-party PCB not imported in release 17.2-2016
6 \3 i6 v0 m) D5 s1758296 APD DXF_IF DXF OUT: Rounded rectangle pads mirrored incorrectly
) N8 N. V. |' N# `+ F1756040 APD IMPORT_DATA The 'die text in' command ignores values after the decimal point
2 T3 |$ H+ f. t/ x7 r1727206 APD SHAPE Merging two shapes results in an incorrect shape( T, K; N7 g* L5 Z. J2 b; i
1753682 CONCEPT_HDL CONSTRAINT_MG Constraint Manager stops responding while cross probing DE-HDL+ p+ g4 ^3 X7 \ {: P( t) p
1721334 CONCEPT_HDL CORE dsreportgen not able to resolve gated part on schematic
$ K+ c' N7 R' K1747559 CONCEPT_HDL CORE Copying a logic symbol without a part table entry results in ERROR(SPCODD-53)
/ w5 \3 ?1 ?% m" q4 q) M1749644 CONCEPT_HDL CORE In release 17.2-2016 Hotfix 019, 'align components' is not working on Windows 8 and DE-HDL crashes; U( H, a8 K! S! ~$ T, |; O7 m, h
1746910 CONCEPT_HDL GLOBALCHANGE Global Component Change unable to identify part data when using schematic pick option9 Z. C: ^2 l! T/ X0 \5 k+ a, ?
1743572 FLOWS PROJMGR Project Manager displays incorrect values in Project Setting
7 s' v" Q# n' K, V1724124 FSP DESIGN_EXPLOR Provide TCL command to filter design connectivity window
5 H+ N6 o( @2 o1719105 FSP GUI Tabular sorting not working in FPGA System Planner
, x) \: A2 T& |- _. @0 `1755750 PCB_LIBRARIAN GRAPHICAL_EDI In release 17.2-2016, unable to delete _N pins in PDV Symbol Editor
* j& f! G# k1 Z. O" K; w7 o, R- X% y1722993 PCB_LIBRARIAN IMPORT_CSV Part Developer crashes while importing part information stored in a .csv file
% W* H7 n6 @9 H9 {) u1758856 SIP_LAYOUT 3D_VIEWER Correct the spelling error in the 3D Viewer Design Configuration window
/ |8 V* F" v! c1755179 SIP_LAYOUT ARTWORK PCB Editor crashes when creating Gerber files
% L+ f2 @2 \2 B9 z1 e2 z8 A1743511 SIP_LAYOUT MANUFACTURING Package Design Integrity shows non-redundant padstacks in the Redundant Padstacks check |
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