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本帖最后由 紫菁 于 2017-9-14 16:05 编辑
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转 Hotfix_SPB17.20.015_wint_1of1
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5 x8 E, @& m5 O2 l8 W @% Y! fFixed CCRs: SPB 17.2 HF0151 t3 [8 I# z1 W/ m! j0 t1 p% v$ u
03-16-2017- f. B9 E2 ]% E1 ?/ P
========================================================================================================================================================1 m1 W& Q$ v" a. n/ q+ ]
CCRID Product ProductLevel2 Title( z2 T9 x9 W: Y) |4 [
========================================================================================================================================================0 y' g5 ~* X" G, @3 u
1653366 allegro_EDITOR INTERFACES Unable to attach step model to symbol- D. F9 B) N1 n. i; M. T
1671760 ALLEGRO_EDITOR INTERFACES Step package mapping window unable to display step model& H% e) K" W& R0 ^2 ^
1706879 ALLEGRO_EDITOR MANUFACT Trace gets moved to dielectric layer after using the Gloss function
, k! |$ j7 J- F ^. g$ D1708685 ALLEGRO_EDITOR MANUFACT Incomplete ncdrill holes data in drl file
% i* t; `3 |, L' h" O: Z3 ^- P# Y1712057 ALLEGRO_EDITOR PAD_EDITOR Changing text size and restarting padstack Editor results in incorrectly scaled forms' C8 Y0 ~1 h* e
1709335 ALLEGRO_EDITOR SCHEM_FTB Cannot import netlist from attached design; d2 j1 h7 w0 Q& Z% [
1687329 ALLEGRO_EDITOR SHAPE Shape is not voiding uniformly when component is rotated in 30 degrees8 I3 Q! Z5 M" ?( Q
1698539 ALLEGRO_EDITOR SHAPE A thin shape is left when dv_fixfullcontact is enabled.
5 a6 {1 O5 T. Z: k/ L, P% ]1620210 ALLEGRO_EDITOR UI_GENERAL Need to run PCB Editor from both 17.2-2016 and 16.6 releases simultaneously3 o: H; z4 g4 |
1687819 ALLEGRO_EDITOR UI_GENERAL Change in Region and Language settings of Windows impacts decimal character in Padstack Editor- J' B! a6 b5 |% @
1699326 ALLEGRO_EDITOR UI_GENERAL Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not: b+ j _. C M$ V* I
1711341 ALLEGRO_EDITOR UI_GENERAL Incorrect pad size in Padstack Editor when the German regional settings are used. z* ]. P* q. t
1712496 ALLEGRO_EDITOR UI_GENERAL Padstack Editor shows incorrect values when using comma and 3 decimal places
" |2 b1 j1 @* }* e1714744 ALLEGRO_EDITOR UI_GENERAL Using comma instead of dot as integer separator results in incorrect diameter value
# a6 D9 l" @+ @" ?7 k) G: r; f1715714 ALLEGRO_EDITOR UI_GENERAL If the 'Decimal places' field is set to 3, values in PAD Designer change automatically* R5 g( g c! v$ e9 l
1713292 APD WIREBOND Allegro Package Designer crashes when adding wire to a die pad0 C1 p3 R' n6 S9 ?
1710973 ASDA PACKAGER Unable to export Allegro SDA project to PCB Layout
j9 G6 K0 |$ ?5 T+ C9 u1698697 concept_HDL COPY_PROJECT Copy project corrupts the .dcf file8 J# c; i$ o9 ~
1705401 CONCEPT_HDL CORE Alignment issues while pasting signal names in 16.6 Hotfix 084 J" a \, a* a: w
1707116 CONCEPT_HDL CORE SIG_NAME is placed on non-grid position
. h' r! _4 A: O; a2 j2 D5 o7 l1710486 CONCEPT_HDL CORE Rename Signal places sig_name at an incorrect position for an unnamed net$ I1 _, X; ^& ^6 u: S3 Y
1667786 CONSTRAINT_MGR XNET_DIFFPAIR Parts with NO_XNET_CONNECTION getting extracted into SigXplorer
0 ?$ a! T; p3 \8 O' d4 o9 A1709508 SIG_INTEGRITY REPORTS Allegro Sigrity SI crashes when running a reflection simulation
! J& ~- C( O; Y4 D% {) J. a% z; k1710097 SIP_LAYOUT DIE_STACK_EDI The IY option of the 'move and stretch wire' command moves the die to incorrect coordinates
3 O0 R$ @$ j' d1712964 SIP_LAYOUT SYMBOL SiP Layout crashes when using Renumber Pins in Symbol Edit application mode
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转：Hotfix_SPB17.20.014_wint_1of1.exe 链接：http://pan.baidu.com/s/1jHFB2Pg 密码：mxnk$ b1 B% G! `2 B6 p
Fixed CCRs: SPB 17.2 HF0148 @5 W5 H& I: L8 `
========================================================================================================================================================
3 v5 G7 a% [8 K0 j4 dCCRID Product ProductLevel2 Title+ c7 e# ]- I2 C! d
======================================================================================================================================================== R! ]% }5 A M# @; I: n& [: b
1691828 ADW COMPONENT_BRO Part Information Manager displays incorrect data related to attributes on relationships {$ }2 P/ a( r v. s: T, X# ?" J
1700963 ALLEGRO_EDITOR DATABASE Running the 'slide' command results in the cline segment losing connectivity6 f: |3 m4 {, Z& e( `
1685502 ALLEGRO_EDITOR INTERFACES The Export - PDF command fails to export the TOP etch subclass with error code SPMHGE-268
6 l3 P% H9 c( X! j' }' G! }& z1644643 ALLEGRO_EDITOR MANUFACT The NC drill legend does not match the drill customization data& _$ h; `3 Q9 P
1700557 ALLEGRO_EDITOR MANUFACT DXF output does not contain drill figure data0 z& R1 ?8 |; w b$ D" i
1660252 ALLEGRO_EDITOR NC NC Drill file generated with errors
! v1 x" J# ? z) ^1677775 ALLEGRO_EDITOR NC Merging of drills not retained in database.
! W6 b. }- I1 }$ o1701554 ALLEGRO_EDITOR SHAPE Shape spacing clearance is not updated unless the shape vertex is deleted
; V5 K/ ^2 P" O$ v6 l# u1704669 ALLEGRO_EDITOR SHAPE Route Keepin is not getting created at a specific location
, N3 I+ z- B, A8 B2 }- g; L' i1685995 ALLEGRO_EDITOR skill All film sequence numbers are returned as 0 when using the SKILL function axlGetParam1 O& W- O0 R6 i' {& V2 {
1621336 ALLEGRO_EDITOR UI_GENERAL Changing the color visibility does not refresh the screen color immediately
4 S+ [2 {& }- b8 k% z1668817 ALLEGRO_EDITOR UI_GENERAL Changing the visibility or the color on the canvas in release 17.2-2016 takes longer than release 16.6
" J7 M/ u. d! _1671268 ALLEGRO_EDITOR UI_GENERAL Visibility Window: There is a noticeable lag when enabling etch, via, and pin on a specific layer one by one
% K% C- P. n$ j2 g; k1690691 ALLEGRO_EDITOR UI_GENERAL Reports not generating if the 'allegro_html_qt' environment variable is disabled
$ |: R/ C0 o( r( {! B1709903 ALLEGRO_EDITOR UI_GENERAL Toggling layer visibility does not change the display until the mouse pointer is moved5 L! c6 i6 I8 N7 E( @: \. \9 \8 W* N, A
1647596 APD EXPORT_DATA Allegro Package Designer crashes when trying to export board-level components" Y5 ^) [% L7 S0 b3 u
1688035 APD OTHER Significant difference seen in the percentage of metal between the Metal Usage reports of positive and negative layers
: ^! s) i8 r7 U4 V# M* V2 {1690777 CONCEPT_HDL CHECKPLUS Rules Checker returns an error when the value of the PACK_TYPE property is in lowercase
: R, S1 l7 W( H3 ]- N1695987 CONCEPT_HDL CORE $PN placement in DE-HDL during part development is not following mouse placement
' g; z& n. g2 H) b: k2 h- D1700873 CONCEPT_HDL CORE With duplicate part table files, running the Assign Power Pins command crashes DE-HDL without any message
$ I# w. g' D+ V/ p1702703 CONCEPT_HDL CORE Location of $PN in DE-HDL Symbol Editor is not as precise as it was in 17.2 Hotfix 011
/ v% }5 L w2 m+ t$ s1705999 CONCEPT_HDL CORE Signal naming is not working correctly in SPB 17.2
. v: ^/ R" y& P& x; `1677489 CONCEPT_HDL CREFER CRefer points to incorrect page numbers when there are page mismatches in the logical and physical page numbers
. ^' f1 t! G9 |5 {& H/ V1698259 CONSTRAINT_MGR CONCEPT_HDL Unstable $LOCATION property in release 17.2-2016
1 u7 z* W5 v' U: V/ h1702537 CONSTRAINT_MGR CONCEPT_HDL ECSet mapping errors reported after removing the signal models on an upreved design4 O7 L- q& c- f, R$ R0 {8 c
1703981 CONSTRAINT_MGR TECHFILE Importing a technology file (.tcf) results in packaging errors
0 i1 b6 @) H: @+ V. p/ a6 X1673115 ECW INTEGRATION Import from external data sources (Integrations) truncates input values to 128 characters6 u, W8 U6 N& V+ X) A7 w( |
1699395 FSP FPGA_SUPPORT Selecting a QSF part name in the FPGA Properties window crashes FSP6 P4 U0 q9 e9 e5 W* i
1704353 INSTALLATION DOWNLOAD_MGR Selecting 'View' in Download Manager results in error, 'Object Reference not set to an instance of an object'; a8 i8 R+ P. T5 _& m8 l8 `
1705265 INSTALLATION DOWNLOAD_MGR Problem installing orcad Library Builder from Download Manager
o# P4 r% X! n. M% z$ V1646635 PDN_ANALYSIS PCB_PI PCB Editor uses 'powerdc.exe' to launch PowerDC instead of the 'powerdc' script( l9 F2 g4 c7 F/ d
y" r. {1 l! s4 p( J# ?1 zcadence OrCAD and Allegro 17.20.013 Hotfix链接：http://pan.baidu.com/s/1kVmHGZ9 密码：smsv
& S2 u( g3 x4 ]+ N" p8 e. ]Fixed CCRs in SPB 17.2 HF013
5 o1 k, U2 b( T+ \2 r: o========================================================================================================================================================
4 p$ \+ e/ Q6 M5 W/ ~# B. BCCRID Product ProductLevel2 Title
$ M/ a+ M1 F8 e5 x. Z+ y" [' F========================================================================================================================================================' j5 r# m. L7 X) J( ]
1567741 ADW COMPONENT_BRO The PPL_list never gets read when using a saveconf.ctr located in the global site.cpm
4 s+ m/ _* F. h2 d5 T; \1697109 ALLEGRO_EDITOR ARTWORK Artwork not showing padstacks for the soldermask layer
4 |; p( o" Q, ~% {; J1682297 ALLEGRO_EDITOR DATABASE Derived padstack and associated padshapes not updated when design is upreved for compatibility with the current version
9 H0 u; C2 P' c/ a+ B& {$ ?1697309 ALLEGRO_EDITOR DATABASE PCB Editor 17.2 uprev changes NC pins from non-plated to plated
1 t2 w& n$ N% z z7 C& k1698624 ALLEGRO_EDITOR DATABASE Opening 16.6 board in 17.2 converts non-plated holes to plated9 W8 W( t& w6 b- y
1697092 ALLEGRO_EDITOR OTHER axlDBViaStack crashes PCB Editor session and corrupts the board
6 P0 q* Z" ?- U) o9 h1 q9 H$ U1687819 ALLEGRO_EDITOR UI_GENERAL Change in Region and Language settings of Windows impacts decimal character in Padstack Editor2 h: u6 K7 I/ r. N+ ~1 s
1696637 ALLEGRO_EDITOR UI_GENERAL Padstack Editor uses Region and Language settings for the decimal symbol; a* Y# E2 Y+ ]! g% ]. t. H8 K
1699326 ALLEGRO_EDITOR UI_GENERAL Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not
& p6 _: U# D& C/ b$ |7 Y" }1616138 ALTM_TRANSLATOR PCB_EDITOR Board file imported from third-party tool to PCB Editor has the shapes but not the components
. l$ o) l3 t( z8 R+ s1666020 ALTM_TRANSLATOR PCB_EDITOR Board converted from a third-party tool to PCB Editor has missing components' _: a3 ^0 S1 H( m# O$ o9 D
1690448 CAPTURE CORRUPT_DESIG Corrupt design: nets in this design are not displayed when running Edit - Browse - Nets
5 J3 u! }; r- [7 _4 w1690455 CAPTURE CORRUPT_DESIG Corrupt design: all the nets in this design are not displayed when running Edit - Browse - Nets: l) _9 v0 {' Z! @ ?. e6 I
1684180 CONCEPT_HDL CORE Message should indicate that the user needs to reload the design after setting SET STICKY_OFF
* S/ t' v& W. i' ~8 v1695987 CONCEPT_HDL CORE $PN placement in DE-HDL during part development is not following mouse placement+ z; g8 m. V: S) M
1688287 CONSTRAINT_MGR DATABASE PCB Editor crashing while adding a net to a net group.
, w- Z; J. I1 i( p7 t( g' u' F1675013 ORBITIO ALLEGRO_SIP_I Failed to import brd file6 t1 v7 J9 k' V1 d( x5 m; b% a, m C
1698968 SIP_LAYOUT 3D_VIEWER 3D viewer shows keepin and not design outline.8 a4 w% @4 D, y: N, W
1699884 SIP_LAYOUT ASSY_RULE_CHE SiP Layout crashes on using Assembly Rules Checker
( s5 U' n6 P* a; I5 Q X1689969 SIP_LAYOUT DIE_EDITOR SiP Layout crashes when moving dies using relative coordinates
D$ c! {. W Y+ U0 B0 h, l* A2 T7 D1696239 SIP_LAYOUT DIE_EDITOR When using the Die-stack Editor to move and stretch wires, SiP Layout crashes
6 V& o6 h: A9 Z* B& W+ j1695372 SIP_LAYOUT REPORTS Running the Metal Usage reports fails on the Primary side.2 f. e7 P$ P% S# j" C T% \
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发表于 2017-2-26 17:05
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发表于 2017-2-26 20:26
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