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本帖最后由 紫菁 于 2017-9-14 16:05 编辑
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5 K0 |& @$ n9 T& w0 F转 Hotfix_SPB17.20.015_wint_1of15 E0 t+ l, B8 U( T* s4 a
* P1 n9 Y5 X* n% P& ]Fixed CCRs: SPB 17.2 HF015
3 E3 V( Y5 y! w( ^: X' {03-16-2017
, T+ F0 B' T0 z+ O4 {* t( m) ^( q========================================================================================================================================================2 n6 J, ?! b0 Z9 N7 b; i4 g
CCRID Product ProductLevel2 Title
- s3 L& n- y9 H) ^. z========================================================================================================================================================
! b ]3 Z% d4 A* h3 r3 x$ I1653366 allegro_EDITOR INTERFACES Unable to attach step model to symbol
0 `" k9 E! u5 M& ]4 y- d$ {1671760 ALLEGRO_EDITOR INTERFACES Step package mapping window unable to display step model
& A. L. `$ q" W, s0 |$ B1706879 ALLEGRO_EDITOR MANUFACT Trace gets moved to dielectric layer after using the Gloss function
! k8 |& e3 Q, n& H3 p1708685 ALLEGRO_EDITOR MANUFACT Incomplete ncdrill holes data in drl file. ^4 ^7 O4 v9 D3 j/ j3 o. C
1712057 ALLEGRO_EDITOR PAD_EDITOR Changing text size and restarting padstack Editor results in incorrectly scaled forms1 |! y9 Z; t( I4 t- \
1709335 ALLEGRO_EDITOR SCHEM_FTB Cannot import netlist from attached design
- Y4 U0 u8 t. w2 S5 }5 Y' X. N1687329 ALLEGRO_EDITOR SHAPE Shape is not voiding uniformly when component is rotated in 30 degrees
' y4 c' F1 F1 T# K1698539 ALLEGRO_EDITOR SHAPE A thin shape is left when dv_fixfullcontact is enabled.
1 N( ~9 ^- ?# ~' _+ C6 D1620210 ALLEGRO_EDITOR UI_GENERAL Need to run PCB Editor from both 17.2-2016 and 16.6 releases simultaneously: Y# i" n' G) ?
1687819 ALLEGRO_EDITOR UI_GENERAL Change in Region and Language settings of Windows impacts decimal character in Padstack Editor8 i, T8 y n6 ]' c& j2 y
1699326 ALLEGRO_EDITOR UI_GENERAL Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not
; u! F7 [& M) P8 _7 g1711341 ALLEGRO_EDITOR UI_GENERAL Incorrect pad size in Padstack Editor when the German regional settings are used; B" g" l3 m. t) G
1712496 ALLEGRO_EDITOR UI_GENERAL Padstack Editor shows incorrect values when using comma and 3 decimal places; u1 c6 B# p; `: B, k/ ^6 J q
1714744 ALLEGRO_EDITOR UI_GENERAL Using comma instead of dot as integer separator results in incorrect diameter value/ Q$ y# t# i' y. c2 p
1715714 ALLEGRO_EDITOR UI_GENERAL If the 'Decimal places' field is set to 3, values in PAD Designer change automatically$ N7 t5 `& _) s% u1 D: [# F
1713292 APD WIREBOND Allegro Package Designer crashes when adding wire to a die pad
. h: x% P( S- X1 j8 d. ]+ M1710973 ASDA PACKAGER Unable to export Allegro SDA project to PCB Layout4 R. Z. E9 G* P. O) }! W
1698697 concept_HDL COPY_PROJECT Copy project corrupts the .dcf file
5 L) W, B ]3 U& A1705401 CONCEPT_HDL CORE Alignment issues while pasting signal names in 16.6 Hotfix 084
7 \: O! \' {+ M1 C# o+ E& G1707116 CONCEPT_HDL CORE SIG_NAME is placed on non-grid position/ Y* n9 h6 J$ M( R% x; i" X
1710486 CONCEPT_HDL CORE Rename Signal places sig_name at an incorrect position for an unnamed net3 G+ ]( W3 t" b- ~
1667786 CONSTRAINT_MGR XNET_DIFFPAIR Parts with NO_XNET_CONNECTION getting extracted into SigXplorer
3 S2 s3 Y5 f4 g5 o. W* e) L" y1 c1709508 SIG_INTEGRITY REPORTS Allegro Sigrity SI crashes when running a reflection simulation
8 y! }6 Z4 i$ A2 X+ I/ X, @1710097 SIP_LAYOUT DIE_STACK_EDI The IY option of the 'move and stretch wire' command moves the die to incorrect coordinates
6 h6 d5 o6 i9 S4 e! J4 G1712964 SIP_LAYOUT SYMBOL SiP Layout crashes when using Renumber Pins in Symbol Edit application mode
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4 `9 z( j. ] j转：Hotfix_SPB17.20.014_wint_1of1.exe 链接：http://pan.baidu.com/s/1jHFB2Pg 密码：mxnk& S" i' l' J" D& W
Fixed CCRs: SPB 17.2 HF014
& Y: \0 F Z5 U3 D7 n% ^========================================================================================================================================================" X; T6 ~9 W0 d5 ~- N) ]
CCRID Product ProductLevel2 Title
: Q {) h* }5 d) b========================================================================================================================================================
o1 ~& o3 r) y1691828 ADW COMPONENT_BRO Part Information Manager displays incorrect data related to attributes on relationships
% s+ M/ E, }% J; ~) Z1700963 ALLEGRO_EDITOR DATABASE Running the 'slide' command results in the cline segment losing connectivity
/ w% E$ s1 A; P }+ ?7 g, k$ a: V1685502 ALLEGRO_EDITOR INTERFACES The Export - PDF command fails to export the TOP etch subclass with error code SPMHGE-268
/ f, `9 h6 P' o, p6 v& ^1644643 ALLEGRO_EDITOR MANUFACT The NC drill legend does not match the drill customization data
& C% s v- `6 A. E% v1700557 ALLEGRO_EDITOR MANUFACT DXF output does not contain drill figure data
+ F$ h( u* u; S T) A/ y; H! Q: V1660252 ALLEGRO_EDITOR NC NC Drill file generated with errors
6 w1 S* I4 c/ w# M. T- s1677775 ALLEGRO_EDITOR NC Merging of drills not retained in database./ ]. s. e9 W1 r; J1 e+ {
1701554 ALLEGRO_EDITOR SHAPE Shape spacing clearance is not updated unless the shape vertex is deleted
; M1 P, V! z \" R" l% J, }0 k1704669 ALLEGRO_EDITOR SHAPE Route Keepin is not getting created at a specific location5 M9 q. T& S% H/ v( z
1685995 ALLEGRO_EDITOR skill All film sequence numbers are returned as 0 when using the SKILL function axlGetParam
& o& t. a( v) z q) F1621336 ALLEGRO_EDITOR UI_GENERAL Changing the color visibility does not refresh the screen color immediately9 j/ T9 N. _+ h
1668817 ALLEGRO_EDITOR UI_GENERAL Changing the visibility or the color on the canvas in release 17.2-2016 takes longer than release 16.6/ e! |' p2 o P' w$ F8 w2 a
1671268 ALLEGRO_EDITOR UI_GENERAL Visibility Window: There is a noticeable lag when enabling etch, via, and pin on a specific layer one by one
% r$ K1 d: T T2 c y5 x0 b4 M1690691 ALLEGRO_EDITOR UI_GENERAL Reports not generating if the 'allegro_html_qt' environment variable is disabled
6 A {6 Q: M& v8 E# \1709903 ALLEGRO_EDITOR UI_GENERAL Toggling layer visibility does not change the display until the mouse pointer is moved% }; Y- R9 X! l: Y
1647596 APD EXPORT_DATA Allegro Package Designer crashes when trying to export board-level components9 t8 N% s. x: O3 l# ~& N" A
1688035 APD OTHER Significant difference seen in the percentage of metal between the Metal Usage reports of positive and negative layers- |; P: r$ }6 f9 W( ~% `( `. k
1690777 CONCEPT_HDL CHECKPLUS Rules Checker returns an error when the value of the PACK_TYPE property is in lowercase
) D5 g. ]/ Y# k5 T1695987 CONCEPT_HDL CORE $PN placement in DE-HDL during part development is not following mouse placement
" z0 h, K+ r, Z" U" P1 q1700873 CONCEPT_HDL CORE With duplicate part table files, running the Assign Power Pins command crashes DE-HDL without any message
1 ~4 z2 c- \8 L" i. D" u1702703 CONCEPT_HDL CORE Location of $PN in DE-HDL Symbol Editor is not as precise as it was in 17.2 Hotfix 011& @) D$ @, Z! A* t: @+ L& @* Z8 F
1705999 CONCEPT_HDL CORE Signal naming is not working correctly in SPB 17.2: I- M! X: Q; z2 G, \& W. P
1677489 CONCEPT_HDL CREFER CRefer points to incorrect page numbers when there are page mismatches in the logical and physical page numbers
; c+ G2 X5 M( H3 a1698259 CONSTRAINT_MGR CONCEPT_HDL Unstable $LOCATION property in release 17.2-2016
8 J. w+ c0 g. E2 |' P6 ?# b1702537 CONSTRAINT_MGR CONCEPT_HDL ECSet mapping errors reported after removing the signal models on an upreved design
7 U% ?' Q; s2 G5 S. U1703981 CONSTRAINT_MGR TECHFILE Importing a technology file (.tcf) results in packaging errors8 |% U Z! _$ _0 q. V
1673115 ECW INTEGRATION Import from external data sources (Integrations) truncates input values to 128 characters
. X1 D$ T9 ~9 q, j- G X1699395 FSP FPGA_SUPPORT Selecting a QSF part name in the FPGA Properties window crashes FSP
q2 R: c, k3 q& ~0 T( |8 I1704353 INSTALLATION DOWNLOAD_MGR Selecting 'View' in Download Manager results in error, 'Object Reference not set to an instance of an object'
, i. T, U3 W9 D# p! @, ~* K# |1705265 INSTALLATION DOWNLOAD_MGR Problem installing orcad Library Builder from Download Manager
! z4 {5 M1 I/ O0 h9 u1646635 PDN_ANALYSIS PCB_PI PCB Editor uses 'powerdc.exe' to launch PowerDC instead of the 'powerdc' script R6 N# h- m$ s. G ]; K" W7 p
) Y# {2 X3 M+ E0 ~cadence OrCAD and Allegro 17.20.013 Hotfix链接：http://pan.baidu.com/s/1kVmHGZ9 密码：smsv
6 d7 O4 F8 C l" ?. OFixed CCRs in SPB 17.2 HF013" w5 s' u% f4 h, G2 a
========================================================================================================================================================
6 i! Q- L- S7 [4 V- W$ ]! GCCRID Product ProductLevel2 Title
, j7 \% U3 y: b4 u7 V( v U========================================================================================================================================================
7 @8 d8 v1 K. J+ `1567741 ADW COMPONENT_BRO The PPL_list never gets read when using a saveconf.ctr located in the global site.cpm
s% E2 p% I+ J" h! x7 E. f1697109 ALLEGRO_EDITOR ARTWORK Artwork not showing padstacks for the soldermask layer
9 I9 W1 t+ p; S3 P% h D: _1682297 ALLEGRO_EDITOR DATABASE Derived padstack and associated padshapes not updated when design is upreved for compatibility with the current version8 G. k8 e8 v0 `5 T+ K
1697309 ALLEGRO_EDITOR DATABASE PCB Editor 17.2 uprev changes NC pins from non-plated to plated
7 O8 ~3 }& `% r1698624 ALLEGRO_EDITOR DATABASE Opening 16.6 board in 17.2 converts non-plated holes to plated
- N& t3 p0 z' C4 b) ^1697092 ALLEGRO_EDITOR OTHER axlDBViaStack crashes PCB Editor session and corrupts the board9 z* C- j- E/ f- x0 p
1687819 ALLEGRO_EDITOR UI_GENERAL Change in Region and Language settings of Windows impacts decimal character in Padstack Editor' X5 e' U" F& ]. a1 {8 l1 p4 R% Z
1696637 ALLEGRO_EDITOR UI_GENERAL Padstack Editor uses Region and Language settings for the decimal symbol2 A. G1 ^/ J# z& Q0 H
1699326 ALLEGRO_EDITOR UI_GENERAL Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not6 d7 p, a$ L1 U7 r
1616138 ALTM_TRANSLATOR PCB_EDITOR Board file imported from third-party tool to PCB Editor has the shapes but not the components$ Q8 w4 v7 g6 N4 W( Z, |
1666020 ALTM_TRANSLATOR PCB_EDITOR Board converted from a third-party tool to PCB Editor has missing components
+ k/ C. l! W& x1690448 CAPTURE CORRUPT_DESIG Corrupt design: nets in this design are not displayed when running Edit - Browse - Nets
( `, l+ @8 G: }1690455 CAPTURE CORRUPT_DESIG Corrupt design: all the nets in this design are not displayed when running Edit - Browse - Nets
4 X6 Y8 n: s6 C9 @5 F [! `1684180 CONCEPT_HDL CORE Message should indicate that the user needs to reload the design after setting SET STICKY_OFF+ ^$ ?4 x: E [) h& A; ?$ D
1695987 CONCEPT_HDL CORE $PN placement in DE-HDL during part development is not following mouse placement
- k4 X) f5 |6 e: _1688287 CONSTRAINT_MGR DATABASE PCB Editor crashing while adding a net to a net group.$ m* T. P. B! e# Q
1675013 ORBITIO ALLEGRO_SIP_I Failed to import brd file* w/ H0 ^& _5 {! q7 k+ q8 y& [
1698968 SIP_LAYOUT 3D_VIEWER 3D viewer shows keepin and not design outline.$ J3 E, R% W/ b8 u9 a2 B8 [5 X
1699884 SIP_LAYOUT ASSY_RULE_CHE SiP Layout crashes on using Assembly Rules Checker
8 z) d. }1 F U9 M2 u# _2 f1689969 SIP_LAYOUT DIE_EDITOR SiP Layout crashes when moving dies using relative coordinates
: w( \' T3 i- s6 _$ I5 w6 R* K, v1696239 SIP_LAYOUT DIE_EDITOR When using the Die-stack Editor to move and stretch wires, SiP Layout crashes; O" b- n# _- Q: }
1695372 SIP_LAYOUT REPORTS Running the Metal Usage reports fails on the Primary side.
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发表于 2017-2-26 17:05
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发表于 2017-2-26 20:26
