|
|
EDA365欢迎您登录！
您需要 登录 才可以下载或查看，没有帐号？注册
x
本帖最后由 紫菁 于 2017-9-14 16:05 编辑 # Z) H+ U5 G5 l8 ]2 Q$ ?. o
1 z$ L0 V. ]& k9 |2 i9 o4 [5 _
转 Hotfix_SPB17.20.015_wint_1of1' [& e. Z1 p4 Z3 Q1 }
; f2 c0 z% h: ?+ z! d: K* LFixed CCRs: SPB 17.2 HF015
9 e1 E/ `* y* X4 y; {) r: E; i03-16-2017
0 ^% t0 V5 t p( ~========================================================================================================================================================
1 ^2 y2 G. |8 T8 c) n% {CCRID Product ProductLevel2 Title5 M' g. b$ p8 H% |, o
========================================================================================================================================================1 f6 G! A. n" E3 T! J2 |
1653366 allegro_EDITOR INTERFACES Unable to attach step model to symbol
" l/ U6 o9 t' Y9 w( ?; N/ \1671760 ALLEGRO_EDITOR INTERFACES Step package mapping window unable to display step model
& p' Z/ z% H. _! s; \1706879 ALLEGRO_EDITOR MANUFACT Trace gets moved to dielectric layer after using the Gloss function
m0 k1 W3 a9 `; d! X0 }1708685 ALLEGRO_EDITOR MANUFACT Incomplete ncdrill holes data in drl file$ Z. Q& ]: V2 ] U ^) q
1712057 ALLEGRO_EDITOR PAD_EDITOR Changing text size and restarting padstack Editor results in incorrectly scaled forms: O7 [4 @2 V/ T; C# t% ?& a
1709335 ALLEGRO_EDITOR SCHEM_FTB Cannot import netlist from attached design6 @6 C) Q5 Q# O& q; r1 W
1687329 ALLEGRO_EDITOR SHAPE Shape is not voiding uniformly when component is rotated in 30 degrees! ] `( w! w M0 [, }6 N1 t
1698539 ALLEGRO_EDITOR SHAPE A thin shape is left when dv_fixfullcontact is enabled.2 M; n* o/ g$ f9 r
1620210 ALLEGRO_EDITOR UI_GENERAL Need to run PCB Editor from both 17.2-2016 and 16.6 releases simultaneously
% G# k, A6 H( v9 l' q6 K: {: x1687819 ALLEGRO_EDITOR UI_GENERAL Change in Region and Language settings of Windows impacts decimal character in Padstack Editor. y( q, v. S5 V0 a6 Z
1699326 ALLEGRO_EDITOR UI_GENERAL Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not, B" C1 H: l1 h8 J5 S9 [( |; R% c
1711341 ALLEGRO_EDITOR UI_GENERAL Incorrect pad size in Padstack Editor when the German regional settings are used
- f* K5 t( p% x- X4 Z2 V1712496 ALLEGRO_EDITOR UI_GENERAL Padstack Editor shows incorrect values when using comma and 3 decimal places9 I5 Q9 t6 q+ q, n8 `3 [
1714744 ALLEGRO_EDITOR UI_GENERAL Using comma instead of dot as integer separator results in incorrect diameter value
3 b; g9 p- x5 ~) G5 B* F" W1 W, i1715714 ALLEGRO_EDITOR UI_GENERAL If the 'Decimal places' field is set to 3, values in PAD Designer change automatically
& E, z1 _6 `% O/ L% t7 c2 j/ G; n1713292 APD WIREBOND Allegro Package Designer crashes when adding wire to a die pad
' A& a, ^7 C# X/ {$ R3 ~1710973 ASDA PACKAGER Unable to export Allegro SDA project to PCB Layout8 q* D0 h( i% Y8 v0 J; B# i
1698697 concept_HDL COPY_PROJECT Copy project corrupts the .dcf file6 C% e4 W+ {3 z) |8 K- C3 i- T
1705401 CONCEPT_HDL CORE Alignment issues while pasting signal names in 16.6 Hotfix 0845 a0 i5 Y8 g {6 w( C) |
1707116 CONCEPT_HDL CORE SIG_NAME is placed on non-grid position7 @4 J2 g4 _' O5 S
1710486 CONCEPT_HDL CORE Rename Signal places sig_name at an incorrect position for an unnamed net
D F( o: P2 ^* u2 v+ s9 w1667786 CONSTRAINT_MGR XNET_DIFFPAIR Parts with NO_XNET_CONNECTION getting extracted into SigXplorer
& s {2 W9 S5 k1709508 SIG_INTEGRITY REPORTS Allegro Sigrity SI crashes when running a reflection simulation- h, }* L4 K% F z
1710097 SIP_LAYOUT DIE_STACK_EDI The IY option of the 'move and stretch wire' command moves the die to incorrect coordinates
* o' I' P' r. o# n4 c, r: U# s" P1712964 SIP_LAYOUT SYMBOL SiP Layout crashes when using Renumber Pins in Symbol Edit application mode
( W! O) P8 P( j5 b ' m6 s6 I& `) C8 a5 F7 @
转：Hotfix_SPB17.20.014_wint_1of1.exe 链接：http://pan.baidu.com/s/1jHFB2Pg 密码：mxnk4 E) n8 W% I; E( Q
Fixed CCRs: SPB 17.2 HF014
3 u" e" U4 H$ G+ T: ?( `. ]1 y========================================================================================================================================================& A N( Y" i7 W
CCRID Product ProductLevel2 Title
5 }0 _% G9 g* m========================================================================================================================================================
, ?3 G% c$ h+ C0 b- x2 B2 a) `1691828 ADW COMPONENT_BRO Part Information Manager displays incorrect data related to attributes on relationships& I) d; s0 A8 t' _! S9 d6 D- m
1700963 ALLEGRO_EDITOR DATABASE Running the 'slide' command results in the cline segment losing connectivity0 n4 n7 l, p% e: h" Q
1685502 ALLEGRO_EDITOR INTERFACES The Export - PDF command fails to export the TOP etch subclass with error code SPMHGE-268( x, f; k* U2 ?$ S. O
1644643 ALLEGRO_EDITOR MANUFACT The NC drill legend does not match the drill customization data
" Q. Y3 y; \( I" t- P, g1700557 ALLEGRO_EDITOR MANUFACT DXF output does not contain drill figure data9 N4 W7 D4 u# r3 R
1660252 ALLEGRO_EDITOR NC NC Drill file generated with errors
% K- o; _! d/ n7 T# X1677775 ALLEGRO_EDITOR NC Merging of drills not retained in database.
* V: f( {( S3 u! [8 y1701554 ALLEGRO_EDITOR SHAPE Shape spacing clearance is not updated unless the shape vertex is deleted
: R% ]+ o8 ~3 j8 \ r5 m0 P Z1704669 ALLEGRO_EDITOR SHAPE Route Keepin is not getting created at a specific location+ `7 a: T8 L4 M- S
1685995 ALLEGRO_EDITOR skill All film sequence numbers are returned as 0 when using the SKILL function axlGetParam
# c5 I# s1 Y3 R* q# X9 \1621336 ALLEGRO_EDITOR UI_GENERAL Changing the color visibility does not refresh the screen color immediately
% e6 e( V! s8 j: x" p! v8 e0 _! M1668817 ALLEGRO_EDITOR UI_GENERAL Changing the visibility or the color on the canvas in release 17.2-2016 takes longer than release 16.6
9 A: a$ s' A J- z' z8 [3 ?1671268 ALLEGRO_EDITOR UI_GENERAL Visibility Window: There is a noticeable lag when enabling etch, via, and pin on a specific layer one by one) H5 k( x9 I+ _5 r
1690691 ALLEGRO_EDITOR UI_GENERAL Reports not generating if the 'allegro_html_qt' environment variable is disabled
2 {4 y a6 D0 y% ], [ P1709903 ALLEGRO_EDITOR UI_GENERAL Toggling layer visibility does not change the display until the mouse pointer is moved
- W2 W q0 F, ^% |/ R5 P1647596 APD EXPORT_DATA Allegro Package Designer crashes when trying to export board-level components* t# ]3 ~6 `1 x: W* O4 H
1688035 APD OTHER Significant difference seen in the percentage of metal between the Metal Usage reports of positive and negative layers5 T1 ?! c: g. ~/ _! X7 E
1690777 CONCEPT_HDL CHECKPLUS Rules Checker returns an error when the value of the PACK_TYPE property is in lowercase7 V, Y6 f Z. J2 s- K
1695987 CONCEPT_HDL CORE $PN placement in DE-HDL during part development is not following mouse placement
1 C* j1 x/ r, A% q, F- Y0 E* N1700873 CONCEPT_HDL CORE With duplicate part table files, running the Assign Power Pins command crashes DE-HDL without any message
- g( n' T' @2 q- A1702703 CONCEPT_HDL CORE Location of $PN in DE-HDL Symbol Editor is not as precise as it was in 17.2 Hotfix 011/ _: Y2 D8 E# j
1705999 CONCEPT_HDL CORE Signal naming is not working correctly in SPB 17.2
& G3 e K4 c U5 ?3 M1677489 CONCEPT_HDL CREFER CRefer points to incorrect page numbers when there are page mismatches in the logical and physical page numbers
# R3 X! y: P4 H1698259 CONSTRAINT_MGR CONCEPT_HDL Unstable $LOCATION property in release 17.2-2016* u5 O9 A& V; u3 S" o3 t0 H
1702537 CONSTRAINT_MGR CONCEPT_HDL ECSet mapping errors reported after removing the signal models on an upreved design# n# `; `) V0 ]* ~, E3 A* e
1703981 CONSTRAINT_MGR TECHFILE Importing a technology file (.tcf) results in packaging errors
) L* [. K& j2 s6 C1 B) M U1673115 ECW INTEGRATION Import from external data sources (Integrations) truncates input values to 128 characters8 O/ Z, M) h! E4 ]" q
1699395 FSP FPGA_SUPPORT Selecting a QSF part name in the FPGA Properties window crashes FSP
2 T* b4 L ^2 E/ S: Z" z1704353 INSTALLATION DOWNLOAD_MGR Selecting 'View' in Download Manager results in error, 'Object Reference not set to an instance of an object'
2 z0 V8 Z: R8 U2 Z& [1705265 INSTALLATION DOWNLOAD_MGR Problem installing orcad Library Builder from Download Manager$ S( O% P- Z( y! ?5 X# t
1646635 PDN_ANALYSIS PCB_PI PCB Editor uses 'powerdc.exe' to launch PowerDC instead of the 'powerdc' script
5 j r! \: A% o4 |- G3 n* {$ S! q
; V; e" ]1 O' |5 x; Gcadence OrCAD and Allegro 17.20.013 Hotfix链接：http://pan.baidu.com/s/1kVmHGZ9 密码：smsv
S! u, ~. ~- N4 j. _Fixed CCRs in SPB 17.2 HF013" A; f D% L% Z3 u7 S2 G( F
========================================================================================================================================================5 a5 w9 n F: n; c/ e2 E, ~) W
CCRID Product ProductLevel2 Title7 }# |8 e0 v& s- F
========================================================================================================================================================2 Y4 Q1 W' q1 ]
1567741 ADW COMPONENT_BRO The PPL_list never gets read when using a saveconf.ctr located in the global site.cpm7 `, _) }- j* I* |2 M
1697109 ALLEGRO_EDITOR ARTWORK Artwork not showing padstacks for the soldermask layer3 L. n* l3 D, o
1682297 ALLEGRO_EDITOR DATABASE Derived padstack and associated padshapes not updated when design is upreved for compatibility with the current version
5 c9 r5 \3 N6 ?; R: i3 [! l" N$ J1697309 ALLEGRO_EDITOR DATABASE PCB Editor 17.2 uprev changes NC pins from non-plated to plated2 q( }2 `7 f, i$ `
1698624 ALLEGRO_EDITOR DATABASE Opening 16.6 board in 17.2 converts non-plated holes to plated) g2 G" C1 E' E5 u1 O; i
1697092 ALLEGRO_EDITOR OTHER axlDBViaStack crashes PCB Editor session and corrupts the board
. }0 ]: f5 L. m1687819 ALLEGRO_EDITOR UI_GENERAL Change in Region and Language settings of Windows impacts decimal character in Padstack Editor5 q# T5 E3 C6 e0 ]; P; Z
1696637 ALLEGRO_EDITOR UI_GENERAL Padstack Editor uses Region and Language settings for the decimal symbol8 P+ N. M* M: R! j
1699326 ALLEGRO_EDITOR UI_GENERAL Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not/ c! a' t i3 V" s2 H6 ~+ g0 }
1616138 ALTM_TRANSLATOR PCB_EDITOR Board file imported from third-party tool to PCB Editor has the shapes but not the components; ?5 b) Z$ }. ~
1666020 ALTM_TRANSLATOR PCB_EDITOR Board converted from a third-party tool to PCB Editor has missing components
" p' v. |; [; I6 D4 l( J. c2 T5 w& R8 i1690448 CAPTURE CORRUPT_DESIG Corrupt design: nets in this design are not displayed when running Edit - Browse - Nets
' d2 \+ _% F/ T0 G* }1690455 CAPTURE CORRUPT_DESIG Corrupt design: all the nets in this design are not displayed when running Edit - Browse - Nets5 e4 [/ z2 N. K9 b6 v8 Z* ]* L
1684180 CONCEPT_HDL CORE Message should indicate that the user needs to reload the design after setting SET STICKY_OFF$ s t0 h% H `& c
1695987 CONCEPT_HDL CORE $PN placement in DE-HDL during part development is not following mouse placement
6 _& W' }' Y& _1 `1688287 CONSTRAINT_MGR DATABASE PCB Editor crashing while adding a net to a net group.0 g5 f: }% s2 ]3 H8 V+ O
1675013 ORBITIO ALLEGRO_SIP_I Failed to import brd file% I9 [- T4 s( d* ^. C: t* e
1698968 SIP_LAYOUT 3D_VIEWER 3D viewer shows keepin and not design outline.
3 S! s, M, g6 ~9 ^1699884 SIP_LAYOUT ASSY_RULE_CHE SiP Layout crashes on using Assembly Rules Checker
; P( d; M& H8 C: d1689969 SIP_LAYOUT DIE_EDITOR SiP Layout crashes when moving dies using relative coordinates
/ P- Q/ Y( A& K1696239 SIP_LAYOUT DIE_EDITOR When using the Die-stack Editor to move and stretch wires, SiP Layout crashes
$ ^, i8 k* _7 P0 q+ P- `# D8 W1695372 SIP_LAYOUT REPORTS Running the Metal Usage reports fails on the Primary side.
: |1 R: F; H# o: G! Y. b$ S% b
# o8 `$ d- A X% l9 a' W& b
& N9 i3 f1 h* p, c1 H( H9 @
9 E2 [8 F) e" M: H) T
; L4 P9 Z2 i9 J; B0 [ |
评分
-
查看全部评分
|
/1 
发表于 2017-2-26 17:05
收藏
淘帖
支持！
反对！
楼主
发表于 2017-2-26 20:26
6 L, q! Q ]; s$ d) _& z) u- K