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本帖最后由 紫菁 于 2017-9-14 16:05 编辑 0 ~/ H$ P4 u0 _' d0 l( p
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转 Hotfix_SPB17.20.015_wint_1of1
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: e# W" |2 C. a; |5 R9 j! ~6 `; TFixed CCRs: SPB 17.2 HF0155 \( ?! ~& h5 h. G/ b
03-16-2017, E* K1 ?" L3 Z% m4 d; f' |
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CCRID Product ProductLevel2 Title- U$ d* d# ]+ L3 Q' {$ q. P
========================================================================================================================================================
7 o4 U _/ l8 m" j2 K5 x1653366 allegro_EDITOR INTERFACES Unable to attach step model to symbol
6 J% F+ q+ l& w: n$ G1671760 ALLEGRO_EDITOR INTERFACES Step package mapping window unable to display step model
' M' E. B" q/ H! P7 w1706879 ALLEGRO_EDITOR MANUFACT Trace gets moved to dielectric layer after using the Gloss function; ?* l0 B X' b) K* _$ h+ z0 q5 F
1708685 ALLEGRO_EDITOR MANUFACT Incomplete ncdrill holes data in drl file
% ?6 ^3 m4 f% z# h* O1712057 ALLEGRO_EDITOR PAD_EDITOR Changing text size and restarting padstack Editor results in incorrectly scaled forms
3 }+ ], j( y5 D7 o# x, K4 `1709335 ALLEGRO_EDITOR SCHEM_FTB Cannot import netlist from attached design, |5 t3 e ?1 s: \8 A1 L6 t
1687329 ALLEGRO_EDITOR SHAPE Shape is not voiding uniformly when component is rotated in 30 degrees& B4 D6 [- }% @; U$ Z$ h
1698539 ALLEGRO_EDITOR SHAPE A thin shape is left when dv_fixfullcontact is enabled.; w, @( ~5 j8 c5 f
1620210 ALLEGRO_EDITOR UI_GENERAL Need to run PCB Editor from both 17.2-2016 and 16.6 releases simultaneously
1 C4 `- d$ L1 m, \ U3 N4 ]7 }1687819 ALLEGRO_EDITOR UI_GENERAL Change in Region and Language settings of Windows impacts decimal character in Padstack Editor( p! C' R/ Z( u# W
1699326 ALLEGRO_EDITOR UI_GENERAL Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not
* l) b& t' ?: z: d* `# G: ?1711341 ALLEGRO_EDITOR UI_GENERAL Incorrect pad size in Padstack Editor when the German regional settings are used
' b; K" B5 [. Q) F. s1712496 ALLEGRO_EDITOR UI_GENERAL Padstack Editor shows incorrect values when using comma and 3 decimal places
. @4 }* ?6 K/ }" Q1714744 ALLEGRO_EDITOR UI_GENERAL Using comma instead of dot as integer separator results in incorrect diameter value
8 r- F# `% U+ K1 h8 Z. X" ^1 ?. u9 ~1715714 ALLEGRO_EDITOR UI_GENERAL If the 'Decimal places' field is set to 3, values in PAD Designer change automatically
/ a! U- u" h! F/ _6 ^1713292 APD WIREBOND Allegro Package Designer crashes when adding wire to a die pad
$ O3 w; @1 j$ C$ K3 T/ L1 n9 c+ g1710973 ASDA PACKAGER Unable to export Allegro SDA project to PCB Layout0 l6 g7 c. b+ B2 G3 W9 t
1698697 concept_HDL COPY_PROJECT Copy project corrupts the .dcf file
+ t5 z$ n' Z4 x3 C7 `' R( ?$ x. P7 e1705401 CONCEPT_HDL CORE Alignment issues while pasting signal names in 16.6 Hotfix 084% o* v, ^- G O' l1 v" W
1707116 CONCEPT_HDL CORE SIG_NAME is placed on non-grid position* g! f: Y9 H) i1 |1 C
1710486 CONCEPT_HDL CORE Rename Signal places sig_name at an incorrect position for an unnamed net0 a+ w) t2 L1 V5 ?- {' @) H- Y
1667786 CONSTRAINT_MGR XNET_DIFFPAIR Parts with NO_XNET_CONNECTION getting extracted into SigXplorer8 T9 a( b. n: M8 M6 Z' l+ i$ O
1709508 SIG_INTEGRITY REPORTS Allegro Sigrity SI crashes when running a reflection simulation3 f* C) p8 A9 b- R: v. P# e$ x
1710097 SIP_LAYOUT DIE_STACK_EDI The IY option of the 'move and stretch wire' command moves the die to incorrect coordinates1 o+ n5 X# q+ s1 N/ G! [2 k
1712964 SIP_LAYOUT SYMBOL SiP Layout crashes when using Renumber Pins in Symbol Edit application mode
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转：Hotfix_SPB17.20.014_wint_1of1.exe 链接：http://pan.baidu.com/s/1jHFB2Pg 密码：mxnk% h% l/ n# Z- L4 A+ c6 l8 Z, h5 r
Fixed CCRs: SPB 17.2 HF014$ b7 M5 u8 c6 U: v4 Q" o
========================================================================================================================================================
1 N$ r' }9 a; q; DCCRID Product ProductLevel2 Title/ q. l+ z5 N$ q- G- a
========================================================================================================================================================
7 C4 O9 e: j3 E$ j# B2 N/ R1691828 ADW COMPONENT_BRO Part Information Manager displays incorrect data related to attributes on relationships
3 e, F2 }! ?6 r4 C1700963 ALLEGRO_EDITOR DATABASE Running the 'slide' command results in the cline segment losing connectivity) \: }( L$ O1 {. j+ }
1685502 ALLEGRO_EDITOR INTERFACES The Export - PDF command fails to export the TOP etch subclass with error code SPMHGE-2685 Y2 \, W) a, y5 ~ a0 }# s! A
1644643 ALLEGRO_EDITOR MANUFACT The NC drill legend does not match the drill customization data1 q) |$ J- m0 x) |- K
1700557 ALLEGRO_EDITOR MANUFACT DXF output does not contain drill figure data8 ?6 }, G/ U$ e! Q
1660252 ALLEGRO_EDITOR NC NC Drill file generated with errors
A! | E; S0 \- ^! f+ _1677775 ALLEGRO_EDITOR NC Merging of drills not retained in database.
/ D! T1 u8 j \' b" U* c/ w% ?$ [ t1701554 ALLEGRO_EDITOR SHAPE Shape spacing clearance is not updated unless the shape vertex is deleted% D& o7 j; d6 L9 ^1 {
1704669 ALLEGRO_EDITOR SHAPE Route Keepin is not getting created at a specific location# I B& U# B5 J* ~- C: q; I4 }
1685995 ALLEGRO_EDITOR skill All film sequence numbers are returned as 0 when using the SKILL function axlGetParam( l7 o+ S, b! T/ Y
1621336 ALLEGRO_EDITOR UI_GENERAL Changing the color visibility does not refresh the screen color immediately& ~: h; y- @1 F7 [7 O) z
1668817 ALLEGRO_EDITOR UI_GENERAL Changing the visibility or the color on the canvas in release 17.2-2016 takes longer than release 16.6
) f9 L( z3 s d J. t3 @" B& d1671268 ALLEGRO_EDITOR UI_GENERAL Visibility Window: There is a noticeable lag when enabling etch, via, and pin on a specific layer one by one
$ d+ x# Q) Y) ^. R! b5 N1690691 ALLEGRO_EDITOR UI_GENERAL Reports not generating if the 'allegro_html_qt' environment variable is disabled
3 V# A. I/ j, r' S& j9 S& q% a: ~1709903 ALLEGRO_EDITOR UI_GENERAL Toggling layer visibility does not change the display until the mouse pointer is moved
; B( z- K+ l' x- i% K* [" G0 |1647596 APD EXPORT_DATA Allegro Package Designer crashes when trying to export board-level components6 r" O0 V, U# Y0 W( L
1688035 APD OTHER Significant difference seen in the percentage of metal between the Metal Usage reports of positive and negative layers
1 u8 s. k% {) m1690777 CONCEPT_HDL CHECKPLUS Rules Checker returns an error when the value of the PACK_TYPE property is in lowercase
" |2 C$ I* k8 E2 g( p A1695987 CONCEPT_HDL CORE $PN placement in DE-HDL during part development is not following mouse placement7 f! K8 F9 A0 J3 h- ]4 ?: a
1700873 CONCEPT_HDL CORE With duplicate part table files, running the Assign Power Pins command crashes DE-HDL without any message
. Y; ^! k9 P3 }1702703 CONCEPT_HDL CORE Location of $PN in DE-HDL Symbol Editor is not as precise as it was in 17.2 Hotfix 011
( b- W7 _( ]# f( t4 r* q- j1705999 CONCEPT_HDL CORE Signal naming is not working correctly in SPB 17.2
- F0 A! E3 ]3 \4 T; r1677489 CONCEPT_HDL CREFER CRefer points to incorrect page numbers when there are page mismatches in the logical and physical page numbers
( x; L3 @- R4 Z4 l5 o1698259 CONSTRAINT_MGR CONCEPT_HDL Unstable $LOCATION property in release 17.2-2016) D+ j9 {. Q6 G
1702537 CONSTRAINT_MGR CONCEPT_HDL ECSet mapping errors reported after removing the signal models on an upreved design
9 Q; G$ z( W, U: n+ \* I! B2 b) A1703981 CONSTRAINT_MGR TECHFILE Importing a technology file (.tcf) results in packaging errors
( L. Z( u5 y0 h3 T2 P) B1673115 ECW INTEGRATION Import from external data sources (Integrations) truncates input values to 128 characters
& F( x4 U1 I' e* }6 Z5 V1699395 FSP FPGA_SUPPORT Selecting a QSF part name in the FPGA Properties window crashes FSP
# n3 d6 v" t) R5 M# z3 s1704353 INSTALLATION DOWNLOAD_MGR Selecting 'View' in Download Manager results in error, 'Object Reference not set to an instance of an object'
# h3 j* E& f' s! S1705265 INSTALLATION DOWNLOAD_MGR Problem installing orcad Library Builder from Download Manager ~. j9 s5 g' e" c5 l8 e( i
1646635 PDN_ANALYSIS PCB_PI PCB Editor uses 'powerdc.exe' to launch PowerDC instead of the 'powerdc' script# f$ w" h) |' X7 d& S. d: h
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cadence OrCAD and Allegro 17.20.013 Hotfix链接：http://pan.baidu.com/s/1kVmHGZ9 密码：smsv# l0 Z/ d5 h. C+ G3 v% f
Fixed CCRs in SPB 17.2 HF013( z. Z% G0 S4 g5 i
========================================================================================================================================================
$ s1 B- q" A* |' JCCRID Product ProductLevel2 Title9 q* T$ Q5 ^9 E5 b
========================================================================================================================================================/ _2 w8 O) M. F& X- N; v4 L
1567741 ADW COMPONENT_BRO The PPL_list never gets read when using a saveconf.ctr located in the global site.cpm1 \. z t' w6 H* `1 z' g% h
1697109 ALLEGRO_EDITOR ARTWORK Artwork not showing padstacks for the soldermask layer2 f9 `6 c9 ~) m7 F3 y) d; d# U! x, h
1682297 ALLEGRO_EDITOR DATABASE Derived padstack and associated padshapes not updated when design is upreved for compatibility with the current version
) O- q1 }% C1 f' C! P. K$ M1697309 ALLEGRO_EDITOR DATABASE PCB Editor 17.2 uprev changes NC pins from non-plated to plated
" e1 a( E, U' u" @7 B8 Z1698624 ALLEGRO_EDITOR DATABASE Opening 16.6 board in 17.2 converts non-plated holes to plated( X7 ]4 K, M6 ?! E H: N: I7 r
1697092 ALLEGRO_EDITOR OTHER axlDBViaStack crashes PCB Editor session and corrupts the board/ [# `7 W/ C I& N$ u6 c ^% ~
1687819 ALLEGRO_EDITOR UI_GENERAL Change in Region and Language settings of Windows impacts decimal character in Padstack Editor6 S5 @! A. @: @" E9 D
1696637 ALLEGRO_EDITOR UI_GENERAL Padstack Editor uses Region and Language settings for the decimal symbol
2 K% h( n- K! v( U% {6 [* ]3 D1699326 ALLEGRO_EDITOR UI_GENERAL Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not
# m0 P |4 Q3 C4 m1616138 ALTM_TRANSLATOR PCB_EDITOR Board file imported from third-party tool to PCB Editor has the shapes but not the components
2 r& A9 T5 a z/ Y- j" I8 U1666020 ALTM_TRANSLATOR PCB_EDITOR Board converted from a third-party tool to PCB Editor has missing components9 g; F9 m+ Z$ K1 E+ D
1690448 CAPTURE CORRUPT_DESIG Corrupt design: nets in this design are not displayed when running Edit - Browse - Nets
. r6 ~2 W7 ?, W; C4 A1690455 CAPTURE CORRUPT_DESIG Corrupt design: all the nets in this design are not displayed when running Edit - Browse - Nets* i9 H( e/ b4 u) p
1684180 CONCEPT_HDL CORE Message should indicate that the user needs to reload the design after setting SET STICKY_OFF" o$ x$ U9 K, a8 z* h4 s
1695987 CONCEPT_HDL CORE $PN placement in DE-HDL during part development is not following mouse placement& x8 ?9 j2 P5 K+ Q) S
1688287 CONSTRAINT_MGR DATABASE PCB Editor crashing while adding a net to a net group.
1 j j3 W8 i$ r9 d k1675013 ORBITIO ALLEGRO_SIP_I Failed to import brd file! Q1 X0 m& U" D- q
1698968 SIP_LAYOUT 3D_VIEWER 3D viewer shows keepin and not design outline." n2 F3 [( Q8 M
1699884 SIP_LAYOUT ASSY_RULE_CHE SiP Layout crashes on using Assembly Rules Checker. h, \/ q; Q, K' E; |9 ?9 O+ `
1689969 SIP_LAYOUT DIE_EDITOR SiP Layout crashes when moving dies using relative coordinates; N# D, F& k X% _& [- q3 D
1696239 SIP_LAYOUT DIE_EDITOR When using the Die-stack Editor to move and stretch wires, SiP Layout crashes
4 R% i+ N9 \8 s9 L' @( K9 R& f1695372 SIP_LAYOUT REPORTS Running the Metal Usage reports fails on the Primary side.
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发表于 2017-2-26 17:05
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楼主
发表于 2017-2-26 20:26
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