|
|
EDA365欢迎您登录！
您需要 登录 才可以下载或查看，没有帐号？注册
x
本帖最后由 紫菁 于 2017-9-14 16:05 编辑
5 E# V; p( l1 `( C+ O8 @
9 w' g# p2 G) N% n转 Hotfix_SPB17.20.015_wint_1of1
% c( E* w- v d# Z0 ?/ T2 P* X$ y5 b/ P& o, P
Fixed CCRs: SPB 17.2 HF015
6 m4 z$ [& N; Q# w+ R- k2 j7 S03-16-2017
% W/ k9 X2 T0 P8 r========================================================================================================================================================
7 k! ~( ~0 O& d5 h) MCCRID Product ProductLevel2 Title
2 J1 s4 d! w5 \4 l3 s========================================================================================================================================================/ m8 k$ w4 k0 }$ A; Z- X
1653366 allegro_EDITOR INTERFACES Unable to attach step model to symbol) M2 y( V+ d3 T: S
1671760 ALLEGRO_EDITOR INTERFACES Step package mapping window unable to display step model1 y/ \, q' b7 l! [0 G6 V1 ^
1706879 ALLEGRO_EDITOR MANUFACT Trace gets moved to dielectric layer after using the Gloss function
9 [* { z; `% W9 J: C1708685 ALLEGRO_EDITOR MANUFACT Incomplete ncdrill holes data in drl file
# @5 A3 x+ V" Y; e1712057 ALLEGRO_EDITOR PAD_EDITOR Changing text size and restarting padstack Editor results in incorrectly scaled forms( j8 {+ D2 O# V$ m$ \3 ]
1709335 ALLEGRO_EDITOR SCHEM_FTB Cannot import netlist from attached design# Q: p( g" X. K; a5 ], [
1687329 ALLEGRO_EDITOR SHAPE Shape is not voiding uniformly when component is rotated in 30 degrees2 w1 U+ [2 w' d) e9 s
1698539 ALLEGRO_EDITOR SHAPE A thin shape is left when dv_fixfullcontact is enabled.9 ]7 v' Y P h7 v4 \- S
1620210 ALLEGRO_EDITOR UI_GENERAL Need to run PCB Editor from both 17.2-2016 and 16.6 releases simultaneously6 L |6 n; w( U
1687819 ALLEGRO_EDITOR UI_GENERAL Change in Region and Language settings of Windows impacts decimal character in Padstack Editor( b! j% _1 \1 _; K2 h
1699326 ALLEGRO_EDITOR UI_GENERAL Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not
- n* Y2 l5 f: O# k U1711341 ALLEGRO_EDITOR UI_GENERAL Incorrect pad size in Padstack Editor when the German regional settings are used# ~5 o X. U! ], i: [
1712496 ALLEGRO_EDITOR UI_GENERAL Padstack Editor shows incorrect values when using comma and 3 decimal places
$ ]/ c0 n0 r2 W1714744 ALLEGRO_EDITOR UI_GENERAL Using comma instead of dot as integer separator results in incorrect diameter value
4 F& i3 o3 P) m1 }8 P5 l1715714 ALLEGRO_EDITOR UI_GENERAL If the 'Decimal places' field is set to 3, values in PAD Designer change automatically
8 ]- B+ l8 Q% z4 @4 i4 n1713292 APD WIREBOND Allegro Package Designer crashes when adding wire to a die pad
2 e! t1 B! R: n( a: q1710973 ASDA PACKAGER Unable to export Allegro SDA project to PCB Layout
" ?' ?# E+ H; C+ d9 H9 [0 N- S: `1698697 concept_HDL COPY_PROJECT Copy project corrupts the .dcf file' i# I" P5 O" {7 x4 Q" g' S
1705401 CONCEPT_HDL CORE Alignment issues while pasting signal names in 16.6 Hotfix 084
1 q' x4 F$ \3 Z1707116 CONCEPT_HDL CORE SIG_NAME is placed on non-grid position a. f, W _1 c, Z/ m6 o9 b
1710486 CONCEPT_HDL CORE Rename Signal places sig_name at an incorrect position for an unnamed net4 S8 j- r/ L" U T8 w
1667786 CONSTRAINT_MGR XNET_DIFFPAIR Parts with NO_XNET_CONNECTION getting extracted into SigXplorer
, Y+ H3 Z7 P7 Y* n# i6 u. i' I, w1709508 SIG_INTEGRITY REPORTS Allegro Sigrity SI crashes when running a reflection simulation. `& L0 x+ C0 q3 V2 Y
1710097 SIP_LAYOUT DIE_STACK_EDI The IY option of the 'move and stretch wire' command moves the die to incorrect coordinates
% E; `1 G+ z' c, t% ~4 X1712964 SIP_LAYOUT SYMBOL SiP Layout crashes when using Renumber Pins in Symbol Edit application mode3 x+ [; S0 Q. ~$ Z* }1 X
1 B' l& t; Z. a7 f* Y; ^0 ~" r
转：Hotfix_SPB17.20.014_wint_1of1.exe 链接：http://pan.baidu.com/s/1jHFB2Pg 密码：mxnk
, H# e6 f6 v9 u% d% aFixed CCRs: SPB 17.2 HF014& A; S. d' I. o- p2 u* T+ W+ c# f; Y4 C
========================================================================================================================================================
: u8 c9 @6 \% i+ y+ T% n+ eCCRID Product ProductLevel2 Title
! L/ V1 M# L( }. E |# o8 d========================================================================================================================================================& W. ] y! E; Q8 c" \* f2 u# d; v
1691828 ADW COMPONENT_BRO Part Information Manager displays incorrect data related to attributes on relationships
9 j0 G; S$ Q# i5 S1700963 ALLEGRO_EDITOR DATABASE Running the 'slide' command results in the cline segment losing connectivity0 N7 _+ t3 h2 F* h% X; `+ b6 s
1685502 ALLEGRO_EDITOR INTERFACES The Export - PDF command fails to export the TOP etch subclass with error code SPMHGE-2686 t* I" l/ o+ A7 Z
1644643 ALLEGRO_EDITOR MANUFACT The NC drill legend does not match the drill customization data* i' I( w8 f4 b% p
1700557 ALLEGRO_EDITOR MANUFACT DXF output does not contain drill figure data
/ S) g, A' _! y& T7 {4 R1660252 ALLEGRO_EDITOR NC NC Drill file generated with errors1 c0 ?1 g) T7 r' E( N' R9 |* i% k
1677775 ALLEGRO_EDITOR NC Merging of drills not retained in database.
# y# A) E' v) N% x' O: R1701554 ALLEGRO_EDITOR SHAPE Shape spacing clearance is not updated unless the shape vertex is deleted
g) @; ~+ ` U: n- m0 ~2 K6 g2 P& n/ b1704669 ALLEGRO_EDITOR SHAPE Route Keepin is not getting created at a specific location# I9 q8 [+ d+ Y$ V
1685995 ALLEGRO_EDITOR skill All film sequence numbers are returned as 0 when using the SKILL function axlGetParam7 O0 I0 u* U" @8 B& z0 c6 i+ e
1621336 ALLEGRO_EDITOR UI_GENERAL Changing the color visibility does not refresh the screen color immediately
, x; R- l; i: w( U+ L1668817 ALLEGRO_EDITOR UI_GENERAL Changing the visibility or the color on the canvas in release 17.2-2016 takes longer than release 16.6) I7 Y3 A4 k4 F/ t, P2 ]
1671268 ALLEGRO_EDITOR UI_GENERAL Visibility Window: There is a noticeable lag when enabling etch, via, and pin on a specific layer one by one
0 e2 J; o% A8 H; S. K) N! T5 m+ u1690691 ALLEGRO_EDITOR UI_GENERAL Reports not generating if the 'allegro_html_qt' environment variable is disabled
]; _ A' j2 k# v. A2 q5 ~1709903 ALLEGRO_EDITOR UI_GENERAL Toggling layer visibility does not change the display until the mouse pointer is moved
$ Y4 ]9 I) h2 Y# a' n. M* r4 V2 [0 J1647596 APD EXPORT_DATA Allegro Package Designer crashes when trying to export board-level components
$ b* X$ J% Y6 u+ ]8 ~: W+ O1 c0 j1688035 APD OTHER Significant difference seen in the percentage of metal between the Metal Usage reports of positive and negative layers# d' l; k: W. t
1690777 CONCEPT_HDL CHECKPLUS Rules Checker returns an error when the value of the PACK_TYPE property is in lowercase( o. h/ R4 f6 y$ h
1695987 CONCEPT_HDL CORE $PN placement in DE-HDL during part development is not following mouse placement5 t0 B: Y+ S+ o8 }3 \- T P
1700873 CONCEPT_HDL CORE With duplicate part table files, running the Assign Power Pins command crashes DE-HDL without any message
. E. d0 z: I/ n& {: c1702703 CONCEPT_HDL CORE Location of $PN in DE-HDL Symbol Editor is not as precise as it was in 17.2 Hotfix 011
+ h5 k. Z: y6 N2 K6 K* y& E) Z1705999 CONCEPT_HDL CORE Signal naming is not working correctly in SPB 17.2
' m8 v' d7 I/ W% y: p! D1677489 CONCEPT_HDL CREFER CRefer points to incorrect page numbers when there are page mismatches in the logical and physical page numbers$ X# A( H& \! k8 {
1698259 CONSTRAINT_MGR CONCEPT_HDL Unstable $LOCATION property in release 17.2-20161 o# f. L" ]1 p, H2 H \
1702537 CONSTRAINT_MGR CONCEPT_HDL ECSet mapping errors reported after removing the signal models on an upreved design6 n, q9 S6 x' H% b3 V
1703981 CONSTRAINT_MGR TECHFILE Importing a technology file (.tcf) results in packaging errors
: Q: C- }; A1 U6 M5 d3 Q1673115 ECW INTEGRATION Import from external data sources (Integrations) truncates input values to 128 characters
9 {7 u, A6 z& L7 s1 B4 K8 G1699395 FSP FPGA_SUPPORT Selecting a QSF part name in the FPGA Properties window crashes FSP, k$ m$ d3 I4 Q" j7 |* ^$ T
1704353 INSTALLATION DOWNLOAD_MGR Selecting 'View' in Download Manager results in error, 'Object Reference not set to an instance of an object'
% H0 R$ o$ B1 z3 M/ v1705265 INSTALLATION DOWNLOAD_MGR Problem installing orcad Library Builder from Download Manager% x2 H) i% y2 a
1646635 PDN_ANALYSIS PCB_PI PCB Editor uses 'powerdc.exe' to launch PowerDC instead of the 'powerdc' script
6 o8 i/ U# g+ f. P1 \) U% h+ f+ D- f6 M, ^5 ~) `
cadence OrCAD and Allegro 17.20.013 Hotfix链接：http://pan.baidu.com/s/1kVmHGZ9 密码：smsv
( W' l& m3 s6 r& u j+ d2 a, ^Fixed CCRs in SPB 17.2 HF013
8 Q( t. r. p' ~. Z p7 j========================================================================================================================================================
9 p7 U5 d% Z3 i; i& DCCRID Product ProductLevel2 Title1 j) f1 g! H% F+ l0 K
========================================================================================================================================================
1 {6 N8 T' Z# c( u5 m6 t) o7 d5 U3 T: w1567741 ADW COMPONENT_BRO The PPL_list never gets read when using a saveconf.ctr located in the global site.cpm
6 n' f' j; `6 u9 D" T1697109 ALLEGRO_EDITOR ARTWORK Artwork not showing padstacks for the soldermask layer/ d& N! L% Y, n! b0 b
1682297 ALLEGRO_EDITOR DATABASE Derived padstack and associated padshapes not updated when design is upreved for compatibility with the current version5 \( z! |% k! c) _3 S$ {3 |
1697309 ALLEGRO_EDITOR DATABASE PCB Editor 17.2 uprev changes NC pins from non-plated to plated
: R/ w" p( V( g- }& C' n1698624 ALLEGRO_EDITOR DATABASE Opening 16.6 board in 17.2 converts non-plated holes to plated( S4 o* n& p u, \ P
1697092 ALLEGRO_EDITOR OTHER axlDBViaStack crashes PCB Editor session and corrupts the board$ B) Y Q) Y3 X! x/ q; K
1687819 ALLEGRO_EDITOR UI_GENERAL Change in Region and Language settings of Windows impacts decimal character in Padstack Editor' p6 d$ |0 h2 ~% p* ~( J: q
1696637 ALLEGRO_EDITOR UI_GENERAL Padstack Editor uses Region and Language settings for the decimal symbol2 |5 G2 A- @7 s0 i5 a8 v
1699326 ALLEGRO_EDITOR UI_GENERAL Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not
2 w3 Z( J' L4 g6 K1616138 ALTM_TRANSLATOR PCB_EDITOR Board file imported from third-party tool to PCB Editor has the shapes but not the components
8 n. H# f( d2 K8 g. n% L1666020 ALTM_TRANSLATOR PCB_EDITOR Board converted from a third-party tool to PCB Editor has missing components
, ^4 L7 q) _4 @' {) t3 `5 f9 a! R1690448 CAPTURE CORRUPT_DESIG Corrupt design: nets in this design are not displayed when running Edit - Browse - Nets
9 i& Y t( ^8 b9 z' F/ w1690455 CAPTURE CORRUPT_DESIG Corrupt design: all the nets in this design are not displayed when running Edit - Browse - Nets
+ t% d. u6 B: q( q1684180 CONCEPT_HDL CORE Message should indicate that the user needs to reload the design after setting SET STICKY_OFF
( V: P/ B, |1 |3 ~ D( Q4 y; T5 [/ w1695987 CONCEPT_HDL CORE $PN placement in DE-HDL during part development is not following mouse placement& @) ]' s: d7 ^1 g0 ? z
1688287 CONSTRAINT_MGR DATABASE PCB Editor crashing while adding a net to a net group.- }) x# @, u$ Q
1675013 ORBITIO ALLEGRO_SIP_I Failed to import brd file& O" y( V! B. e
1698968 SIP_LAYOUT 3D_VIEWER 3D viewer shows keepin and not design outline.
, I9 E% O X+ y( Z9 K* N1699884 SIP_LAYOUT ASSY_RULE_CHE SiP Layout crashes on using Assembly Rules Checker, S4 c/ L. |# L: r" @- T
1689969 SIP_LAYOUT DIE_EDITOR SiP Layout crashes when moving dies using relative coordinates
; W$ p& O% e, r7 Q# ]1696239 SIP_LAYOUT DIE_EDITOR When using the Die-stack Editor to move and stretch wires, SiP Layout crashes. p7 c( K% |7 e' @" s+ M' y* v
1695372 SIP_LAYOUT REPORTS Running the Metal Usage reports fails on the Primary side.
! t0 V& @1 S7 X% `0 M5 S: a( D) Y: \- u# w5 Y) S
3 w7 }5 Q9 n) K; v! Q U+ R% u- @' f4 ?# Z, Y: R
- s1 k4 i6 L" l' i8 L1 O |
评分
-
查看全部评分
|
/1 
发表于 2017-2-26 17:05
收藏
淘帖
支持！
反对！
楼主
发表于 2017-2-26 20:26
- v9 @6 x" |+ t9 B. T: B