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LBSALE[10]LBSALEMIXED-SIGNAL AND DSP DESIGN TECHNIQUES; \" P+ V0 C3 n0 v3 z7 z! H+ D6 n _
SECTION 1
B: j( n0 F8 g1 C; H# Y, @/ UINTRODUCTION* U$ w" x# U% j( ^0 e# q' p8 R6 f1 D
SECTION 2
* u; q. W9 o$ \' T$ m5 ]( O6 TSAMPLED DATA SYSTEMS
. `1 m) L; H4 Z Discrete Time Sampling of Analog Signals
! A! A+ B% E* d9 j, k. ` ADC and DAC Static Transfer Functions and DC Errors
5 I8 |- E# r* v" M! g/ p AC Errors in Data Converters" J; d" A2 A# S
DAC Dynamic PeRFormance
8 a u. b; O3 S( t4 xSECTION 3
- j; g {0 U5 d1 {( O6 t& ^ADCs FOR DSP APPLICATIONS
% h% L$ D+ e6 q, l8 x Successive Approximation ADCs
, E9 p) ?& ]" ^$ O+ _2 S) h: x Sigma-Delta ADCs
# C. {8 T1 H+ ^/ x: b Flash Converters
/ e7 C9 p/ Y e! D/ p Subranging (Pipelined) ADCs
5 W3 q4 |) |0 M7 f6 J& m Bit-Per-Stage (Serial, or Ripple) ADCs; g/ H# Y8 }% D! H( _2 C1 s- u ]
SECTION 49 ~& Q* P& U, |& M" ^) T) W
DACs FOR DSP APPLICATIONS. j; O9 d. V, y* S( z
DAC Structures
/ B# \. S8 C3 @& s4 V Low Distortion DAC Architectures
4 e1 ]7 ?* X+ A/ Y7 U' m' z1 u DAC Logic
% V. h( G$ C- R- w' o8 { Sigma-Delta DACs9 Y W0 n$ U8 W, F+ {
Direct Digital Synthesis (DDS)
+ f ?7 G N) L9 R# FSECTION 5
, t- W2 ~, s* x9 |7 N7 y. lFAST FOURIER TRANSFORMS" K; y3 V$ V6 V2 ]7 Y2 I) S
The Discrete Fourier Transform
6 D, h5 F# Q9 o2 v2 i: O The Fast Fourier Transform
; Y! ?$ h* l5 [7 J# r( X! a& P) j FFT Hardware Implementation and Benchmarks( |. M- p. x9 w6 J; ^
DSP Requirements for Real Time FFT Applications
# K$ B: @ w) i9 ~- r d- _: Q Spectral Leakage and Windowing
" B; K! r Z! {1 \SECTION 6
; ?9 _ V+ s. v) R3 @DIGITAL FILTERS
* p# Q" Z; U; p6 k, w$ ?, D Finite Impulse Response (FIR) Filters
) _% W/ [8 h3 T6 P6 T& G Infinite Impulse Response (IIR) Filters5 n8 P* t- S8 m
Multirate Filters! Y0 N4 q+ v6 _" v( _$ h
Adaptive Filters# ~9 ~# |+ i4 I2 E, N- p* I5 J7 u" g
SECTION 70 Z; E2 b" ^8 S y, d2 [
DSP HARDWARE
& A- R) H# P; M) K) B/ H* n& {$ s Microcontrollers, Microprocessors, and Digital Signal
& l2 O+ M$ l5 Y" }9 K1 L+ [4 b+ v3 iProcessors (DSPs)) A3 _1 E* W/ \" T/ M1 V7 r/ |: X
DSP Requirements# X& `) E% y/ O" m6 S
ADSP-21xx 16-Bit Fixed-Point DSP Core
! O$ c5 O3 z9 R9 [ Fixed-Point Versus Floating Point, A7 i! E. A9 o, o
ADI SHARC® Floating Point DSPs( c( i, _6 i8 J3 n* _
ADSP-2116x Single-Instruction, Multiple Data (SIMD)$ D, H: L+ e& N Y9 O+ A ?# }
Core Architecture( L/ R: f0 H; R8 A4 c
TigerSHARC™: The ADSP-TS001 Static Superscalar
, t6 E0 d1 p0 K7 B ODSP5 u* J( G, c! k3 l" @; ^
DSP Benchmarks; f( j& q' n7 `7 L6 W% t5 t* ]
DSP Evaluation and Development Tools* p* b) g/ Z( d& Y& y1 d
SECTION 86 k6 p3 i4 T$ \, w' p# d
INTERFACING TO DSPs# l) w4 n4 s1 F
Parallel Interfacing to DSP Processors: Reading Data( @$ N: d% K1 ~7 u1 `" i0 J# l$ n
From Memory-Mapped Peripheral ADCs
, R/ B7 L; B G. `; P Parallel Interfacing to DSP Processors: Writing Data to
/ X, V) l6 q' e- K# p9 `' mMemory-Mapped DACs5 h' _0 p$ T. @. R
Serial Interfacing to DSP Processors$ O! F+ ^0 h/ `) A
Interfacing I/O Ports, Analog Front Ends, and Codecs to* k z! w2 m4 o7 p2 h) G1 s4 b" k
DSPs" w# J( n. F3 }; w" E( @
DSP System Interface C) u- n3 L3 p1 l/ P! t h' \4 T7 \* F
SECTION 9
( K$ |6 V" Y9 F5 Y7 p' v( ]5 s. cDSP APPLICATIONS
2 G1 t, Z- H7 K High Performance Modems for Plain Old Telephone. x8 o, T0 _- u: _% D0 V
Service (POTS). g A: T" h- U/ R7 l
Remote Access Server (RAS) Modems% g! {: R. B1 D ]- o# P( ?. g% @
ADSL (Assymetric Digital Subscriber Line)
* Z% |& G- c5 W3 F; X Digital Cellular Telephones
' I4 M5 S+ i& M R GSM Handset Using SoftFone™ Baseband Processor2 B+ Y- ?8 U- @2 K1 \3 n
and Othello™ Radio8 ?' I9 ` Q9 [6 D+ F' Q* M- K
Analog Cellular Basestations
) D) c5 T3 Q; r+ M. F6 M) ` Digital Cellular Basestations
$ B% c/ s" ^+ w( v Motor Control! e1 X8 a* S8 Z
Codecs and DSPs in Voiceband and Audio Applications- ? q7 X4 H& R, q6 V7 C
A Sigma-Delta ADC with Programmable Digital Filter3 ~8 [$ t3 r4 E$ N, w) N6 ^
SECTION 10
% f0 s& I9 b0 Y3 xHARDWARE DESIGN TECHNIQUES
1 Y5 z) u3 q) v/ h" {* E Low Voltage Interfaces
; d, K% x$ \7 o0 i Grounding in Mixed Signal Systems; n7 A0 s$ ^3 H. m/ ?
Digital Isolation Techniques) K4 A; V' C- h5 l
Power Supply Noise Reduction and Filtering) y) L: E2 w2 V% }* V1 E
Dealing with High Speed Logic
. J7 r7 w) N8 ? [0 L0 @0 y' T2 UINDEX文字 |
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