|
EDA365欢迎您登录!
您需要 登录 才可以下载或查看,没有帐号?注册
x
Since the earliest days of microprocessors, system designers have been plagued by a problem in which the0 O7 [4 O; b" ]7 X
speed of the CPU's operation exceeded the bandwidth of the memory subsystem to which it was connected.% q' l/ L% [+ t4 e: A
To avoid wasting CPU cycles while waiting for the memory to fetch the requested data, the universally0 F$ S+ q, g! f. Z
adopted solution was to use an area of faster (and thus more expensive) memory to cache main memory data.
6 |, }: Q: ?, t2 AThis solution allowed the CPU to operate at its natural speed as long as the data it required was available in
3 G J% O3 a+ q" t6 A* A2 q* |3 Vthe cache. |
|