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Since the earliest days of microprocessors, system designers have been plagued by a problem in which the z) Q5 a; M, v8 M, i: d% O
speed of the CPU's operation exceeded the bandwidth of the memory subsystem to which it was connected.
& m1 S$ o6 P5 w) {, RTo avoid wasting CPU cycles while waiting for the memory to fetch the requested data, the universally
: K2 ?4 H# z4 w2 K- |2 wadopted solution was to use an area of faster (and thus more expensive) memory to cache main memory data.; I( c/ j4 A' y9 s. b
This solution allowed the CPU to operate at its natural speed as long as the data it required was available in- J9 I: o5 k+ E% ]* d; B6 W, W
the cache. |
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