Synthesiable High Performance SDRAM Contoller

Haiting32451

Synthesiable High PeRFormance SDRAM Contoller

* R$ I  G6 k, k, VSynthesiable High Performance SDRAM Contoller
9 ^8 ~( F6 U( h; kSynchronous DRAMs are available in speed grades above 100 MHz using LVTTL I/Os. The
$ p% N9 p+ X  p' rVirtex? series of FPGAs and the Spartan?-II family of FPGAs have many features, such as
1 y8 B; X! c8 h/ D4 Y5 V9 RSelectI/O? resource and the Clock Delay Lock Loop, that make it easy to interface to high
; Q- y, L* \( z4 ]% m4 ?speed Synchronous DRAMs. This application note describes the design and implementation of
a synthesizable, parameterizable, flexible, auto-placed-and-routed synchronous DRAM
, M" W- ]0 W; l9 P+ b' Q6 Z, ]' bcontroller in the Virtex FPGA family. The design can also be implemented with a Spartan-II
device. A 32-bit wide data interface version can run up to 125 MHz when automatically placed
) |( x3 g. |) h( L4 Jand routed in a Virtex -6 speed grade device. Hand placed versions of the design can run even
( A$ G, q5 I" ?1 Gfaster.

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