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Synthesiable High PeRFormance SDRAM Contoller
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, B( H$ c# O. |% t" B& d3 ]0 K. c3 fSynthesiable High Performance SDRAM Contoller
/ n5 i% M; e; _+ |" H% o, x: D L! `' |3 VSynchronous DRAMs are available in speed grades above 100 MHz using LVTTL I/Os. The: U- e8 h; N+ y1 G, d4 F
Virtex? series of FPGAs and the Spartan?-II family of FPGAs have many features, such as- N5 d% b4 I9 @4 }
SelectI/O? resource and the Clock Delay Lock Loop, that make it easy to interface to high8 q- h1 D5 |7 _7 A: C% k! F1 x% ^( Z
speed Synchronous DRAMs. This application note describes the design and implementation of+ P. i l- Y. A# j9 g* J) P$ {; m
a synthesizable, parameterizable, flexible, auto-placed-and-routed synchronous DRAM
2 O( g9 F8 b- {/ Z( ]controller in the Virtex FPGA family. The design can also be implemented with a Spartan-II8 j; p S% b _7 T9 e
device. A 32-bit wide data interface version can run up to 125 MHz when automatically placed
( F, F y: a/ B/ I! land routed in a Virtex -6 speed grade device. Hand placed versions of the design can run even0 o1 b9 @: W8 g: k1 l$ L3 _4 O
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发表于 2016-6-12 10:59
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发表于 2016-6-13 15:22