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SDR新书:Baseband Analog Circuits for Software Defined Radio
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( H* h; `3 y3 r: c* h- U. Y) d6 uAuthor:9 z9 u( e: q/ ^9 Y+ f5 C- I: v S
% t, {- X6 e3 o5 Y% f% D, U, l4 m, IVITO GIANNINI 1 h6 i/ J* U" h% f* ^
JAN CRANINCKX 9 h* }; v3 s2 P$ @ J) R
ANDREA BASCHIROTTO
0 R7 @' ?3 f6 e7 JIMEC, Wireless Research, Leuven, Belgium ' U* [, x1 Y1 K" b4 ^' G
IMEC, Wireless Research, Leuven, Belgium 8 X# }2 d- q, J( [+ \" p. @
University of Salento, Italy) C' n" w4 @) ^1 p
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Contents ' ]1 e3 ]; y% s) X
Dedication v & b4 \, J6 ^! H/ I* _. s
Preface xi 2 `7 t( a& f. f# |$ @& R
Acknowledgments xv
0 @, F1 d' s! u5 @: g1. 4G MOBILE TERMINALS 1 $ _3 B5 X) _/ X
1.1 A Wireless-Centric World 1
: k0 D. o6 \8 p1.2 The Driving Forces Towards 4G Systems 3 $ Q6 \! l5 b7 Z0 P( {
1.3 Basic Architecture For a 4G Terminal 6
+ ~( X# n$ T- J1 g1.4 The Role of Analog Circuits 8 ) u ]* S: }- C7 O0 L
1.5 Energy-Scalable Radio Front End 9
5 V6 u$ x0 p, y8 c( \1.6 Towards Cognitive Radios 11 0 x% G4 W; r9 Z7 _7 P" c
2. SOFTWARE DEFINED RADIO FRONT ENDS 13
7 a8 k/ s% d: z2.1 The Software Radio Architecture 13
" k& N8 n# j. ^* t C8 O5 M2.2 Candidate Architectures for SDR Front Ends 16 0 v0 `- t, H0 _
2.2.1 Heterodyne and digital-IF receivers 17 ; S% t/ V; H4 T9 W, O1 U c
2.2.2 Zero-IF receivers 19
8 s% X5 m f4 h# c) W2.2.3 Digital low-IF receivers 22 7 F/ A7 X2 \) z5 d+ l, X3 [& Z, u7 k
2.2.4 Bandpass sampling receivers 24
; e8 Y3 x/ r9 w& Y2.2.5 Direct RF sampling receivers 26
+ E% E( x! B7 Z7 {. H3 Q. I2 n2.3 SDR Front End Implementation 27
4 H, u* X/ ]' J7 h9 ?' Q2.3.1 LNA and input matching 29 7 l2 Z* B) {) l- N
2.3.2 Frequency synthesizer 30
% d+ V2 Q8 Y" s& q) e* J2.3.3 Baseband signal processing 31 : X* {* y# W3 o8 S% z
2.3.4 Measurements results 31
' W9 s1 r; u2 R c2.4 Digital Calibration of Analog Imperfections 33
. ^5 q. [! i, {& [ @. l- @& V2 o2.4.1 Quadrature imbalance 34
& R4 r( P* s% Z" _- v2.4.2 DC offset 36; k, u ^/ }7 G/ K$ d
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' @9 ?8 m! h5 K. d# R, Y6 E5 {' ZContents
. V9 V) C4 n2 F6 K0 x( t% f2.4.3 Impact of LPF spectral behavior 36 ) s! m1 \( s R i" T
2.5 Conclusions 37
" b9 Q; |4 f' @& E$ O3. LINK BUDGET ANALYSIS IN THE SDR ANALOG
7 x/ x2 z, S, F5 Q6 {; [BASEBAND SECTION 39 ( }% S* H5 v' P' O3 ]; \" E
3.1 Analog Baseband Signal Processing 39
9 h3 c7 F% L) f3.2 Baseband Trade-Offs for Analog to Digital Conversion 40
0 S9 V% T. U. V j3.2.1 Number of poles for the LPF 41
- U" X% y! d0 ?6 X3.2.2 ADC dynamic range 42 % g: S+ ], c/ F' ^# U7 [+ [
3.2.3 Baseband power consumption estimation 47
! G" T R1 y. ^8 }6 H3.3 Multistandard Analog Baseband Specs 48 + `4 z6 U q( B; r% T7 ?( O
3.4 Multimode Low-Pass Filter 49 " f H; k, Z2 Y: Y5 q% R: F4 y
3.4.1 Filter selectivity 50
6 O% g) o$ }! O3.4.2 Filter noise and linearity 54 % N) |% H# z! U3 ]
3.4.3 Filter flexibility planning 56 P+ f& U1 r# i i. r5 E' Q
3.4.4 Cascade of biquadratic sections 59 - G1 D; I9 `" ?( z: Q
3.5 Automatic Gain Control 62 / R$ |3 q, {3 X& r: [3 h
3.6 Conclusions 65
2 p: H/ w! G; _$ f; x- T8 t( \4. FLEXIBLE ANALOG BUILDING BLOCKS 67 . U5 A7 k+ v5 f+ J! c
4.1 Challenges in Analog Design for Flexibility 67 ! H. f7 d4 ?' m4 c& I0 w* x
4.2 A Modular Design Approach 68 : F6 H P! e" D: c, j
4.3 Flexible Operational Amplifiers 70
! o/ Y, v. G8 c# i$ v0 Z4.3.1 Variable current sources 70 3 A: j7 o; i9 |" c
4.3.2 Arrays of operational amplifiers 71
& Y0 e0 w# } Z: n4.4 A Digital-Controlled Current Follower 75
) O% M: S& {. E: B4.5 Flexible Passive Components 75
, Q& b; V, T" f4.6 Flexible Transconductors 77
! h$ l% V; A+ p* J4.7 Flexible Biquadratic Sections 78 * j: Z: \5 B8 H; f
4.7.1 The Active-Gm-RC biquad 79 3 x2 h' W9 @+ N# V, I* b# V$ I
4.8 Conclusions 91 ( `+ i! U% w; c3 D. \
5. IMPLEMENTATIONS OF FLEXIBLE FILTERS FOR SDR
1 H. u' f. Z8 l6 cFRONT END 93 + k8 z: M6 W3 k, f
5.1 State of the Art for Flexible CT Filters 93
! j! F% d: `" r) t9 \5.2 A Reconfigurable UMTS/WLAN Active-Gm-RC LPF 94 B2 z8 X- J8 y: u
5.2.1 Filter architecture 96 ! O- u4 M+ n$ w9 z; E. U! o: p5 [
5.2.2 Automatic RC calibration scheme 97
) a, w7 ?+ V q( ^5.2.3 Measurements results 102
( Y9 h( C1 B' e% @2 rContents
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4 P" l, {/ R! Q* Y# h) T; A3 e! ?' C5.3 LPF and VGA for SDR Front End 105 : D" J! N5 X6 n; G$ c
5.3.1 LPF and VGA architectures 107 0 D' [6 i, K9 ~, @; C
5.3.2 Prototype measurements 111 5 Y( X! h9 w: N* ]& U2 Q
5.4 Conclusions 118
/ U+ P) a' k3 D4 d% `& P2 z; lAcronyms 119 6 X# W' D& R: [& G7 f- Y
List of Figures 123
- k$ ^5 L: W; M; P/ K: O3 o* }9 e" uList of Tables 129
' v7 U) ~6 T b bReferences 131 ) Q1 j# i* p8 A! H: K9 L
Index 139
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