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PCB图进行DRC检测/ a, z$ Y3 Q3 ?! e
选择其中Clearance Constraints Max/Min Width Constraints Short Circuit Constraints 和Un-Routed Nets Constraints 这几项(请大家帮忙看看是什么问题,我是自学的protel,尚不熟练,请指教!谢谢!)
0 \, q! O& z/ e# A结果如下:& q) A1 F; g; A$ `
Processing Rule : Width Constraint (Min=10mil) (Max=10mil) (Prefered=10mil) (On the board ) S9 J, `2 J, I$ b* f, ^/ ]: T
Violation Polygon Arc (6033.874mil,6670.183mil) TopLayer Actual Width = 8mil
3 _* H9 z5 k0 q% q& ~0 x Violation Polygon Arc (6019.943mil,6665.654mil) TopLayer Actual Width = 8mil+ f/ V, M: c6 A+ o$ I
Violation Polygon Arc (6006.011mil,6661.126mil) TopLayer Actual Width = 8mil; d( y3 Y, b! j2 S% Q5 ^
Violation Polygon Arc (5992.08mil,6656.597mil) TopLayer Actual Width = 8mil! m' G K4 u8 b1 o6 e
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More than 120 violations detected. DRC stopped!% o2 y3 r b+ h, S; a. t, w
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