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发表于 2016-2-2 23:47
VREF control0 d# A& p8 K4 @1 e
Setup and hold time margin could be reduced if VREF has noise. VREF integrity should be provided by the user to optimize noise margin in the system. The VREF level is expected to track variations in VDDQ , and the peak-to-peak noise should be met with specification: S! N: \% X7 q7 j0 X- Y* l
- 1KΩ±1%/1KΩ±1%/ from VDDQ power panel
- Place a 0.1uF capacitor between VREF and VDDQ
- Place a 0.1uF capacitor between VREF and VSSQ
- VREF should have a minimum trace to reduce inductance
- VREF should keep a distance from other signals to reduce the potential of a decoupling effect
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7 F+ z7 E. k ~6 N1 L1 D還真的有 DRAM Design Guide 這樣教!
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