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本帖最后由 pzt648485640 于 2015-10-18 11:10 编辑 , U8 e$ M7 s$ X; l7 h
4 b2 m2 n5 F" g" [% @2 H* o由于17.0作为过度版;固未做太多更新;应坛友需求所发
$ X5 C- R: H; g& n6 MDATE: 09-04-2015 HOTFIX VERSION: 006
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$ D1 c9 a+ C, R6 f$ E1458272 SIP_LAYOUT ASSY_RULE_CHECK File size increases by factor 4 after ADRC check on a specific customer design; A9 f0 A) Z6 i! p& q" R( I
1460178 allegro_EDITOR INTERFACE_DESIGN PCB Editor crashes on deleting vias or nets2 |& d' B# X' m% b( s
1461387 SIP_LAYOUT skill axlDBRefreshID(nil) removes ID from assigned variable
! @* ]% n" ?/ k" N+ L. d) m7 {1461625 SIP_LAYOUT ASSY_RULE_CHECK Core polygon routines are not creating proper polygons; ADRCs reported: "acute angle", "exposed metal to exposed metal"
; K/ @' H3 X. v# Z: a1464771 SIG_INTEGRITY OTHER Application crashes when extracting Diff Pair topology from Constraint Manager3 I% U; j- Z2 a9 Z, H+ T2 W
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http://pan.baidu.com/s/1gdhBNzl
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9 I+ Z) G' i+ m. h: Y# b: T直连SPB17.02 ~, I1 h$ l" v+ H1 Y
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