Cadence迎来了Hotfix_SPB17.00.002_wint_1of1补丁

pzt648485640

下载：http://pan.baidu.com/s/1gdhBNzl

8 W& W  E: y) e" }6 n- e; R; p/ A DATE: 05-01-2015   HOTFIX VERSION: 002
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/ }1 M+ ]; D0 j: x" N6 b  H) l. C0 r CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
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1315048 allegro_EDITOR INTERFACES       IPC2581 translation inconsistency on negative layer
) j% j# w2 T  @3 j  o3 F 1362745 CONSTRAINT_MGR OTHER            Allegro PCB Editor crashes on opening Constraint Manager with any design
4 B. [2 S. W! U! W- m' } 1373412 ALLEGRO_EDITOR GRAPHICS         SigXP Print Canvas : Via model seems to be filled by black Via box.
- c0 q- W) l) w7 d 1376765 CONSTRAINT_MGR ANALYSIS        SETUP/Hold spreadsheet lists only one pin pair
1399646 ASI_SI         OTHER            Should be able to run mbs2brd with SI/PI base licenses
1400215 SIG_INTEGRITY  REPORTS          cross talk failure on certain nets in PCB SI 16.6
* v7 C, S( A& e$ n6 b& z0 A 1400302 ALLEGRO_EDITOR MANUFACT         Copper Thieving is working differently in SPB16.6 as compared to SPB16.5
1400755 ALLEGRO_EDITOR SHAPE            Updating the shapes on the ATTACHED deisgn causes a short to a pad.
1400813 ALLEGRO_EDITOR SHAPE            PCB Editor crashes when you delete islands from all the layers and save the board
' [) ]5 ~: j4 M! m 1404174 SIP_LAYOUT     OTHER            Creating bounding shapes generates INCORRECT shapes and DRCs
1404184 ALLEGRO_EDITOR INTERFACES       Step package mapping - Save is disabled for certain symbol
1406457 ALLEGRO_EDITOR SCRIPTS          Unable to launch allegro.exe -orcad after update hotfix 046
" y  x; Z0 e! v% X8 ?; ~ 1407123 ALLEGRO_EDITOR OTHER            Lines with zero line width are not being printed in PDF format
1407483 ALLEGRO_EDITOR REFRESH          The 'refresh symbol' command creates an unrouted connection in a fully routed design
1408072 SIP_LAYOUT     OTHER            Net assignment for a BGA component fails on running the File - Import - Netlist-in wizard command.
1410857 ALLEGRO_EDITOR DRC_CONSTR       Diff Pair Uncoupled length DRC gives different results in SPB16.3,  SPB16.5, and SPB16.6.
1413235 ALLEGRO_EDITOR INTERACTIV       Find by Query with Via Structures: GUI freeze
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' Y5 e- J& L* Q2 I' n9 X, Y: v  I DATE: 04-03-2015   HOTFIX VERSION: 001
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) @  Z: ]' K2 w) J' G* F& g/ v! V4 q* _ CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
& U; ^/ a. A4 {7 s+ c2 l ===================================================================================================================================
* F3 m8 `/ U" j1 F: R( e2 ] 491042  concept_HDL    SECTION          Prevent PackagerXL from changing visibility on SEC attribute
' d! ]# @$ ?9 t, Z! x) A' A) g' T+ Y 1205900 ALLEGRO_EDITOR INTERACTIV       additional object polygon-rectangle for "snap to pick"
1327533 SIP_LAYOUT     REPORTS          Metal Usage Report fails
1341177 ALLEGRO_EDITOR PLACEMENT        "Place Replicate Unmatched Component Interface" window size should be increased to show "Matched Component"
3 ]% i5 T5 ?; b, ^. r 1360269 SIP_LAYOUT     REPORTS          Getting incorrect results in the Metal Usage report of SiP Layout when the variable METAL_USAGE_REPORT_NOARCS is set
1361281 ALLEGRO_EDITOR INTERACTIV       Moving stacked vs non-stacked via's should be the same.
' F7 j, t: L% |- I! i6 m 1366525 ALLEGRO_EDITOR INTERACTIV       Add replace via with via structure command to Allegro PCB
2 ?  A6 Y9 z) G. ?' J 1368091 ALLEGRO_EDITOR INTERACTIV       Snap pick to fuction should see fiiled rectangle as a shape
1371510 APD           DATABASE         How to show DRC when tack point of wirebond out of finger boundary
; A2 |- P/ l/ P 1373564 ASI_PI         GUI              Impedance results are incorrect in PFE
1374703 ALLEGRO_EDITOR SHAPE            Inconsistent behavior on shape voiding
( f0 _/ f' v* @. m9 w9 Z2 u 1376851 CONSTRAINT_MGR UI_FORMS         CM workbooks change after simulating
1377555 ALLEGRO_EDITOR DRC_CONSTR       The "Line to SMD Pin Same Net Spacing" DRC toggles everytime we run "Force Update" of Dynamic Shapes.
, w3 e5 b6 m+ G; b6 a/ J 1378032 ALLEGRO_EDITOR REPORTS          Report command and batch mode give different Waived DRC Report results in PCB Editor
0 U' H3 b4 N% l6 g+ E 1378611 ALLEGRO_EDITOR INTERFACES       Enable STEP export to convert the mixed unit into one single unit
0 T6 T6 H& ^" D& Z7 c 1379240 APD            PLACEMENT        Placement gives error regarding the difference in units between the database and symbol, which is not the case
0 u$ _- s* t4 N5 F 1394908 ALLEGRO_EDITOR DATABASE         Database crashes on doing "Show Element" on selected net
1395541 ALLEGRO_EDITOR PLOTTING         Export PDF not correct for Phantom lines
" M* D, I6 U: X; j2 Q  I. E/ ?1 g 1395747 CONSTRAINT_MGR INTERACTIV       Rename refdes causes Allegro to crash. Possibly due to CM being open.
1396915 APD            STREAM_IF        The question about MIRROR geometry function from stream out
1 G) r6 L# Q# p3 A* o2 H, | 1398184 ALLEGRO_EDITOR MANUFACT         Mismatch in backdrill data with IPC-2581 export

allanwang

谢谢楼主分享！

qiuzhang

现在补丁小了好多了，试试

zxpchx

是不是和原来16.6的升级方式一样？

qiuzhang

打上补丁，在运行下破解就行了

zgyzgy

可以转低版本了吗？

pzt648485640

zxpchx 发表于 2015-5-7 13:20
是不是和原来16.6的升级方式一样？

是的
1 |2 \) k" s: P0 Z# E8 N/ t

dzkcool

更新太勤快，希望Cadence能出一个实时联网设计的功能

金志峰

上次论坛不是发过一个? 不是说不是独立的安装文件?

wolfshiao

暫時還沒用到17.0的,
5 o( K7 i% z3 |, d, O/ @; X先下來放著先囉!!
感謝大大的分享了..

penny190

謝謝分享喔

我wo

謝謝分享

xiesonny

这个很赞呀，可惜了，我用17。0有问题。不知道你们有木有，我觉得破解有点问题

viiv9999

感谢，哪位成功了呀！！！！！！！！

czxjuren

安装补丁后，c:\4.png