Cadence迎来了Hotfix_SPB17.00.002_wint_1of1补丁

pzt648485640

下载：http://pan.baidu.com/s/1gdhBNzl
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DATE: 05-01-2015   HOTFIX VERSION: 002
5 w0 J7 `, r! P% H1 ?$ r; A! \) Z ===================================================================================================================================
3 m0 W( {+ I3 h: F CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
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1315048 allegro_EDITOR INTERFACES       IPC2581 translation inconsistency on negative layer
  ?1 I7 F4 d6 _& k( D; D 1362745 CONSTRAINT_MGR OTHER            Allegro PCB Editor crashes on opening Constraint Manager with any design
1373412 ALLEGRO_EDITOR GRAPHICS         SigXP Print Canvas : Via model seems to be filled by black Via box.
1376765 CONSTRAINT_MGR ANALYSIS        SETUP/Hold spreadsheet lists only one pin pair
0 H) }% _$ o* X  J 1399646 ASI_SI         OTHER            Should be able to run mbs2brd with SI/PI base licenses
1400215 SIG_INTEGRITY  REPORTS          cross talk failure on certain nets in PCB SI 16.6
1400302 ALLEGRO_EDITOR MANUFACT         Copper Thieving is working differently in SPB16.6 as compared to SPB16.5
" f/ Q% f2 Y# C& C  C, S$ d* Y 1400755 ALLEGRO_EDITOR SHAPE            Updating the shapes on the ATTACHED deisgn causes a short to a pad.
1400813 ALLEGRO_EDITOR SHAPE            PCB Editor crashes when you delete islands from all the layers and save the board
' l1 C3 v! ^' _' S! a: J2 ?1 k# Q 1404174 SIP_LAYOUT     OTHER            Creating bounding shapes generates INCORRECT shapes and DRCs
# L% `' y3 e1 g' z2 s8 B' n$ T 1404184 ALLEGRO_EDITOR INTERFACES       Step package mapping - Save is disabled for certain symbol
8 j. J/ P8 s' R( I$ F5 Y$ n 1406457 ALLEGRO_EDITOR SCRIPTS          Unable to launch allegro.exe -orcad after update hotfix 046
1407123 ALLEGRO_EDITOR OTHER            Lines with zero line width are not being printed in PDF format
/ x: D7 X. ~# s; c  e: O; Q 1407483 ALLEGRO_EDITOR REFRESH          The 'refresh symbol' command creates an unrouted connection in a fully routed design
1408072 SIP_LAYOUT     OTHER            Net assignment for a BGA component fails on running the File - Import - Netlist-in wizard command.
1410857 ALLEGRO_EDITOR DRC_CONSTR       Diff Pair Uncoupled length DRC gives different results in SPB16.3,  SPB16.5, and SPB16.6.
1413235 ALLEGRO_EDITOR INTERACTIV       Find by Query with Via Structures: GUI freeze

2 R2 Y) i$ o7 o* ^0 U2 I* X DATE: 04-03-2015   HOTFIX VERSION: 001
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CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
===================================================================================================================================
+ f7 U+ C9 h+ z! @" w+ l 491042  concept_HDL    SECTION          Prevent PackagerXL from changing visibility on SEC attribute
1205900 ALLEGRO_EDITOR INTERACTIV       additional object polygon-rectangle for "snap to pick"
1327533 SIP_LAYOUT     REPORTS          Metal Usage Report fails
0 |7 i& \/ R3 g  @5 x4 F 1341177 ALLEGRO_EDITOR PLACEMENT        "Place Replicate Unmatched Component Interface" window size should be increased to show "Matched Component"
- q. ~/ e( G: [ 1360269 SIP_LAYOUT     REPORTS          Getting incorrect results in the Metal Usage report of SiP Layout when the variable METAL_USAGE_REPORT_NOARCS is set
7 X+ [+ l' F  W1 N4 H/ o  B 1361281 ALLEGRO_EDITOR INTERACTIV       Moving stacked vs non-stacked via's should be the same.
! q6 e/ w4 r0 q 1366525 ALLEGRO_EDITOR INTERACTIV       Add replace via with via structure command to Allegro PCB
1368091 ALLEGRO_EDITOR INTERACTIV       Snap pick to fuction should see fiiled rectangle as a shape
3 h. a! {. c: ?7 J 1371510 APD           DATABASE         How to show DRC when tack point of wirebond out of finger boundary
0 }: M7 I/ L$ M; O7 V' M 1373564 ASI_PI         GUI              Impedance results are incorrect in PFE
0 i. M, J$ |6 t( u: p 1374703 ALLEGRO_EDITOR SHAPE            Inconsistent behavior on shape voiding
& I4 E. d1 i: k 1376851 CONSTRAINT_MGR UI_FORMS         CM workbooks change after simulating
$ E! b9 `1 ?; B1 i7 }6 B6 p' a- I( z6 ?  R 1377555 ALLEGRO_EDITOR DRC_CONSTR       The "Line to SMD Pin Same Net Spacing" DRC toggles everytime we run "Force Update" of Dynamic Shapes.
& w& v+ O* M  [8 C  Z. S 1378032 ALLEGRO_EDITOR REPORTS          Report command and batch mode give different Waived DRC Report results in PCB Editor
1378611 ALLEGRO_EDITOR INTERFACES       Enable STEP export to convert the mixed unit into one single unit
, N0 R6 N" O8 h; v& I7 P 1379240 APD            PLACEMENT        Placement gives error regarding the difference in units between the database and symbol, which is not the case
- B& L# \- d8 [1 j 1394908 ALLEGRO_EDITOR DATABASE         Database crashes on doing "Show Element" on selected net
1395541 ALLEGRO_EDITOR PLOTTING         Export PDF not correct for Phantom lines
6 B5 K  U( d* G( B, z, i7 u 1395747 CONSTRAINT_MGR INTERACTIV       Rename refdes causes Allegro to crash. Possibly due to CM being open.
% ]4 Y4 _  s2 X' e: {& i2 B( | 1396915 APD            STREAM_IF        The question about MIRROR geometry function from stream out
1398184 ALLEGRO_EDITOR MANUFACT         Mismatch in backdrill data with IPC-2581 export

allanwang

谢谢楼主分享！

qiuzhang

现在补丁小了好多了，试试

zxpchx

是不是和原来16.6的升级方式一样？

qiuzhang

打上补丁，在运行下破解就行了

zgyzgy

可以转低版本了吗？

pzt648485640

zxpchx 发表于 2015-5-7 13:20
是不是和原来16.6的升级方式一样？

" }1 {. S8 \* ~: ^( }6 ~% Z是的
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dzkcool

更新太勤快，希望Cadence能出一个实时联网设计的功能

金志峰

上次论坛不是发过一个? 不是说不是独立的安装文件?

wolfshiao

暫時還沒用到17.0的,
% c+ D" g" S! @先下來放著先囉!!
: S  U1 W5 K# C4 d* j感謝大大的分享了..

penny190

謝謝分享喔

我wo

謝謝分享

xiesonny

这个很赞呀，可惜了，我用17。0有问题。不知道你们有木有，我觉得破解有点问题

viiv9999

感谢，哪位成功了呀！！！！！！！！

czxjuren

安装补丁后，c:\4.png