对这段文字描述感觉有些困惑

mengzhuhao

对这段文字描述感觉有些困惑
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8.0 Actual "full_case" design problem
The 2-to-4 decoder with enable in Example 12, uses a case statement that is coded without using
+ j- U8 V- j: j- `" iany synthesis directives. The resultant design was a decoder built from 3-input and gates and
inverters. No latch is inferred because all outputs are given a default assignment before the case
statement. For this example, the pre-synthesis and post-synthesis designs and simulations
2 R2 l8 v( K' @$ L( gmatched. The 2-to-4 decoder with enable in Example 13, uses a case statement with the
' }" [8 M' `6 m" z, b"full_case" synthesis directive. Because of this synthesis directive, the enable input (en) was
- P' C) O% k9 `0 r! H3 T; q; ^) Eoptimized away during synthesis and left as a dangling input. The pre-synthesis simulation
results of modules code4a and code4b matched the post-synthesis simulation results of module
6 }& ?: E: X( y9 \* g. o% vcode4a, but did not match the post-synthesis simulation results of module code4b [2].
1 \4 X) ]  V9 @9 L3 R$ K// no full_case
// Decoder built from four 3-input and gates
# H* b: t" U0 G" p: s6 l// and two inverters
2 Z: v9 B/ }' Kmodule code4a (y, a, en);
% r; N" l  P" X* J6 aoutput [3:0] y;
input [1:0] a;
input en;
reg [3:0] y;
always @(a or en) begin
y = 4'h0;
' d6 t& H1 n5 X+ c8 }" V' hcase ({en,a})
3'b1_00: y[a] = 1'b1;
. ~7 p8 T& u! o4 E% Z. I3'b1_01: y[a] = 1'b1;
3'b1_10: y[a] = 1'b1;
3'b1_11: y[a] = 1'b1;
* M3 B7 m2 a) E  Jendcase
end
endmodule
Example 12 - Decoder example with no "full_case" directive
Statistics for case statements in always block at line 9 in file
# B1 \6 j' R2 K9 U: F  x- P0 {'.../code4a.v'
6 L0 _/ K' ~5 y( p===============================================
: a9 s4 K0 W5 n' q3 J| Line | full/ parallel |
4 `  k- F" P4 R! g5 I$ a6 _===============================================
| 12 | no/auto |
===============================================
Figure 19 - Case statement report for Example 12


// full_case example
* i. O( c5 Q3 m: |" w3 O6 D// Decoder built from four 2-input nor gates
// and two inverters
// The enable input is dangling (has been optimized away)
0 i. T- U( k- y" Xmodule code4b (y, a, en);
$ f) F/ C0 J; Ooutput [3:0] y;
input [1:0] a;
+ F8 X! V) l8 e- r5 d' [input en;
# B8 b! [6 S  H* z& q# Oreg [3:0] y;
always @(a or en) begin
" G% @0 D6 y( W; ?y = 4'h0;
case ({en,a}) // synopsys full_case
3'b1_00: y[a] = 1'b1;
3'b1_01: y[a] = 1'b1;
3'b1_10: y[a] = 1'b1;
/ m4 Z, u% K* o# V# F/ i$ q' ^& N$ Z3'b1_11: y[a] = 1'b1;
endcase
( v4 y3 F6 z! t0 V; B  G  gend
endmodule
Example 13 - Decoder example with "full_case" directive
; Q8 [( N# w6 q0 @# ]Warning: You are using the full_case directive with a case statement in which
not all cases are covered
Statistics for case statements in always block at line 10 in file
  h6 ]0 B; S+ z8 g* x! |. z'.../code4b.v'
===============================================
| Line | full/ parallel |
===============================================
| 13 | user/auto |
===============================================
" }- f# D% O# ~/ R8 s' qFigure 20 - Case statement report for Example 13
6 e$ p8 E+ s" ?
谁给解释一下原因呢?
为啥会有差异?