对这段文字描述感觉有些困惑

mengzhuhao

对这段文字描述感觉有些困惑
) g8 O2 D7 D% T4 w

4 n% S) `; o" G; w4 O' c) x4 j% x+ |8.0 Actual "full_case" design problem
The 2-to-4 decoder with enable in Example 12, uses a case statement that is coded without using
  i2 F6 _' |2 oany synthesis directives. The resultant design was a decoder built from 3-input and gates and
inverters. No latch is inferred because all outputs are given a default assignment before the case
& E# B  Q7 t! ?3 W' Q& c- hstatement. For this example, the pre-synthesis and post-synthesis designs and simulations
matched. The 2-to-4 decoder with enable in Example 13, uses a case statement with the
"full_case" synthesis directive. Because of this synthesis directive, the enable input (en) was
optimized away during synthesis and left as a dangling input. The pre-synthesis simulation
results of modules code4a and code4b matched the post-synthesis simulation results of module
code4a, but did not match the post-synthesis simulation results of module code4b [2].
8 m8 v6 U# Q! b, B+ Y// no full_case
// Decoder built from four 3-input and gates
// and two inverters
% J6 s1 J" l7 x2 }module code4a (y, a, en);
output [3:0] y;
input [1:0] a;
) H+ |+ D' N% Pinput en;
reg [3:0] y;
always @(a or en) begin
: n0 h2 {. a- }5 W  i2 A& Ty = 4'h0;
case ({en,a})
3'b1_00: y[a] = 1'b1;
) g- H8 e) I7 m3 b' [$ s+ y3'b1_01: y[a] = 1'b1;
3'b1_10: y[a] = 1'b1;
9 a( `4 X3 f! @3'b1_11: y[a] = 1'b1;
* @$ n+ [! r* e& Z2 Kendcase
end
endmodule
Example 12 - Decoder example with no "full_case" directive
( t+ t( t: N; F+ T, q* MStatistics for case statements in always block at line 9 in file
'.../code4a.v'
===============================================
| Line | full/ parallel |
===============================================
| 12 | no/auto |
===============================================
Figure 19 - Case statement report for Example 12
9 f. n- h" ?5 P' t. B

// full_case example
% P- l* G1 w* k  P% r9 x0 v: f// Decoder built from four 2-input nor gates
$ G! ~( O, U6 f8 f! @9 @// and two inverters
// The enable input is dangling (has been optimized away)
- M1 n3 \+ t- \; Emodule code4b (y, a, en);
" E+ g5 O, A6 g  V/ }output [3:0] y;
' Q  L" v: @. I3 d  \  o, W0 g& @" linput [1:0] a;
input en;
reg [3:0] y;
+ F  A& S3 p" h, w6 @: j) a9 halways @(a or en) begin
9 Y9 s) v! _! L" k9 F- }3 U8 f- c  uy = 4'h0;
case ({en,a}) // synopsys full_case
. s8 t2 v2 E$ S3'b1_00: y[a] = 1'b1;
3'b1_01: y[a] = 1'b1;
3'b1_10: y[a] = 1'b1;
3'b1_11: y[a] = 1'b1;
endcase
end
endmodule
' q; p6 o( W8 g& J4 k) qExample 13 - Decoder example with "full_case" directive
Warning: You are using the full_case directive with a case statement in which
not all cases are covered
7 ~$ J! k0 M" \, ?* uStatistics for case statements in always block at line 10 in file
' O! [0 D, B# P'.../code4b.v'
$ s7 ?; X2 F- c' G( g! q, f===============================================
8 E7 r) |  K# w  l| Line | full/ parallel |
===============================================
/ T( x) a1 P4 y  t, ?" A1 d| 13 | user/auto |
===============================================
" }" n4 {1 C+ k( x" P- M  m6 EFigure 20 - Case statement report for Example 13
$ s( j; N1 N& H
谁给解释一下原因呢?
为啥会有差异?