TA的每日心情 | 擦汗 2020-1-14 15:59 |
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签到天数: 1 天 [LV.1]初来乍到
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对这段文字描述感觉有些困惑
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8.0 Actual "full_case" design problem3 q6 _3 t. X' {" H
The 2-to-4 decoder with enable in Example 12, uses a case statement that is coded without using
+ j- U8 V- j: j- `" iany synthesis directives. The resultant design was a decoder built from 3-input and gates and9 k: R0 u" h& e& O# F1 V' V- _
inverters. No latch is inferred because all outputs are given a default assignment before the case$ P( C2 U5 k% C# _
statement. For this example, the pre-synthesis and post-synthesis designs and simulations
2 R2 l8 v( K' @$ L( gmatched. The 2-to-4 decoder with enable in Example 13, uses a case statement with the
' }" [8 M' `6 m" z, b"full_case" synthesis directive. Because of this synthesis directive, the enable input (en) was
- P' C) O% k9 `0 r! H3 T; q; ^) Eoptimized away during synthesis and left as a dangling input. The pre-synthesis simulation( B( w+ Q2 h) Z ]
results of modules code4a and code4b matched the post-synthesis simulation results of module
6 }& ?: E: X( y9 \* g. o% vcode4a, but did not match the post-synthesis simulation results of module code4b [2].
1 \4 X) ] V9 @9 L3 R$ K// no full_case. l/ l- y4 c$ q. n/ _/ X8 F
// Decoder built from four 3-input and gates
# H* b: t" U0 G" p: s6 l// and two inverters
2 Z: v9 B/ }' Kmodule code4a (y, a, en);
% r; N" l P" X* J6 aoutput [3:0] y;# |. l+ f2 ], C1 P* ?& V
input [1:0] a;6 q: ~- F! K* h$ e$ n% M
input en;: O, [2 d- B" C/ K
reg [3:0] y;1 a$ f! g; W+ l$ c' d
always @(a or en) begin. R, {/ s* ]' z. |
y = 4'h0;
' d6 t& H1 n5 X+ c8 }" V' hcase ({en,a})5 t1 o: y& i- P! G% n' N) g
3'b1_00: y[a] = 1'b1;
. ~7 p8 T& u! o4 E% Z. I3'b1_01: y[a] = 1'b1;- B; }; W4 |+ d+ ?+ R: m
3'b1_10: y[a] = 1'b1;4 `3 B9 D# D6 }( b) c! X/ T' E
3'b1_11: y[a] = 1'b1;
* M3 B7 m2 a) E Jendcase, s6 e0 l5 H5 c6 V# F- l4 a" A/ W
end7 T% p( }5 j5 l2 L4 o6 p
endmodule+ q' c, c' E+ y6 L) ~3 ?' Y" P
Example 12 - Decoder example with no "full_case" directive. ?7 Y" [$ L/ }0 J' j
Statistics for case statements in always block at line 9 in file
# B1 \6 j' R2 K9 U: F x- P0 {'.../code4a.v'
6 L0 _/ K' ~5 y( p===============================================
: a9 s4 K0 W5 n' q3 J| Line | full/ parallel |
4 ` k- F" P4 R! g5 I$ a6 _===============================================4 s A: \! {' d
| 12 | no/auto |- O. d. `' [8 W. N8 z* S) B6 \
===============================================% S: c- i0 H1 q) t. r( Z7 B' H! g
Figure 19 - Case statement report for Example 12- t _0 C. h* }( r: W2 e( P
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// full_case example
* i. O( c5 Q3 m: |" w3 O6 D// Decoder built from four 2-input nor gates, e+ k$ W- x$ G! D
// and two inverters/ E7 q- n' X, @3 m, B
// The enable input is dangling (has been optimized away)
0 i. T- U( k- y" Xmodule code4b (y, a, en);
$ f) F/ C0 J; Ooutput [3:0] y;/ X" g( M1 [. K3 o& K4 r
input [1:0] a;
+ F8 X! V) l8 e- r5 d' [input en;
# B8 b! [6 S H* z& q# Oreg [3:0] y;3 N) Z5 Y: N2 D: o+ v& U+ y% h5 \8 s
always @(a or en) begin
" G% @0 D6 y( W; ?y = 4'h0;( [& j% ]1 J( X7 _
case ({en,a}) // synopsys full_case: Y4 \2 j, l. S# j- v1 T
3'b1_00: y[a] = 1'b1;0 H! Z+ D. f2 b' o( b6 U. g
3'b1_01: y[a] = 1'b1;. t7 S' G w$ q& O
3'b1_10: y[a] = 1'b1;
/ m4 Z, u% K* o# V# F/ i$ q' ^& N$ Z3'b1_11: y[a] = 1'b1;4 }2 _8 I9 b' v2 ~2 x7 _5 m
endcase
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endmodule7 E" s; }/ D, b; l
Example 13 - Decoder example with "full_case" directive
; Q8 [( N# w6 q0 @# ]Warning: You are using the full_case directive with a case statement in which" X! r- U5 {! H5 X
not all cases are covered1 C# @1 @( [8 q2 F
Statistics for case statements in always block at line 10 in file
h6 ]0 B; S+ z8 g* x! |. z'.../code4b.v'% k3 R$ o6 F! r k$ s# p( q; u
===============================================; x$ K6 ^# U" r9 C+ l; L+ x
| Line | full/ parallel |) |% s* |' y6 {7 [% j5 a
===============================================4 I5 e1 d0 Q7 A% G, C3 C! I
| 13 | user/auto |" `) |6 t6 ?6 a6 @
===============================================
" }- f# D% O# ~/ R8 s' qFigure 20 - Case statement report for Example 13
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谁给解释一下原因呢?+ Z9 J. X( f4 ` k/ R
为啥会有差异? |
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