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对这段文字描述感觉有些困惑

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    对这段文字描述感觉有些困惑+ Q1 S% y. M' [, s
    & ^' r+ N$ t+ c: {$ B

    ; g( @! b8 `; F4 V0 F$ P" u8.0 Actual "full_case" design problem' B; ]" @) M$ n  _  {( v
    The 2-to-4 decoder with enable in Example 12, uses a case statement that is coded without using
    1 D& T# D4 |0 F0 e2 A& G' t" |any synthesis directives. The resultant design was a decoder built from 3-input and gates and# [; E3 p* f$ x2 K
    inverters. No latch is inferred because all outputs are given a default assignment before the case' X& T7 L2 t( k: }( O
    statement. For this example, the pre-synthesis and post-synthesis designs and simulations2 q# y' c) }) A; J  [% T/ ~
    matched. The 2-to-4 decoder with enable in Example 13, uses a case statement with the
    ' U) f. q& l4 ^6 H; y6 [# P2 v"full_case" synthesis directive. Because of this synthesis directive, the enable input (en) was; u0 z7 U/ R" C8 j2 R+ Z
    optimized away during synthesis and left as a dangling input. The pre-synthesis simulation
    * [3 Q8 D9 S* lresults of modules code4a and code4b matched the post-synthesis simulation results of module) L# u! ]" g; h. ~+ f( G
    code4a, but did not match the post-synthesis simulation results of module code4b [2].) u+ I% r/ L% i
    // no full_case+ T$ D( S; k# Y, c7 E. |- T9 f! `' U
    // Decoder built from four 3-input and gates
    $ Y8 Z" k( ?( l3 p// and two inverters
    6 F- h; f* K' S7 b% dmodule code4a (y, a, en);
    . m3 G/ E7 r8 `$ Moutput [3:0] y;
    , Z; o* R  c, T" O' linput [1:0] a;
    - z( Y/ \- `* f) P/ T$ u2 sinput en;7 \- B; y) Q  U2 N
    reg [3:0] y;" p& o/ q% I$ X9 }
    always @(a or en) begin6 \0 K. D8 @. y! O+ ]% h# M
    y = 4'h0;, H: w! [9 K. Z& [9 r( f; {
    case ({en,a})
    : A% B* G5 P/ Z0 k& V0 Q% z3'b1_00: y[a] = 1'b1;% v! O# t+ J/ g' k1 a. T( z) L
    3'b1_01: y[a] = 1'b1;
    5 f3 g, r! V7 ]+ K1 c3'b1_10: y[a] = 1'b1;& P! M  X% S  E, C+ `; C
    3'b1_11: y[a] = 1'b1;
    3 H; G  J9 H/ s, [endcase4 W0 N' V, f0 T* a: u7 E+ l
    end
    6 {# H% Q' }: g7 H" lendmodule; J  a# h7 {. a+ j3 E# s! |0 E
    Example 12 - Decoder example with no "full_case" directive3 j* C( w' p7 F; S# u3 z7 ^5 w# Y( p$ X
    Statistics for case statements in always block at line 9 in file' P+ _' Y! {5 d& ~) h
    '.../code4a.v'; j; C2 _  f8 ^$ }2 p% M! ?
    ===============================================& v9 ~7 j( h3 n) N3 N" a
    | Line | full/ parallel |
    , y# d! i, }: M; y  H& c2 `! L! D; [===============================================$ {! I/ ^9 h/ t% g
    | 12 | no/auto |
    5 Z8 f( u! J5 d1 C. Z' Y===============================================6 \+ ~& O; H2 `! P% o& r
    Figure 19 - Case statement report for Example 129 [1 z9 P" G/ n5 U1 }

    8 G1 M3 \( i# K
    ( X3 m2 Q, A. b  Q$ O6 r// full_case example
    # Z) w$ U6 a5 Q+ [5 k0 {' L, }* r* ?// Decoder built from four 2-input nor gates: h$ A+ L- i3 [3 V, t, b7 }  A3 X! I* \
    // and two inverters1 W$ L- [: n- `* L# I
    // The enable input is dangling (has been optimized away)
    4 e, a' Y2 l+ h3 z( p5 ]module code4b (y, a, en);) [4 U5 q' u& n
    output [3:0] y;& O9 N$ p/ l' P1 U6 H
    input [1:0] a;+ U1 c" p0 Q" J6 i
    input en;
    . m  e# s$ u/ S2 P) [9 mreg [3:0] y;; C! Y! D5 ]& Y
    always @(a or en) begin9 w) q3 _- L: a7 y( b
    y = 4'h0;+ W- i1 }5 D. |1 R% O2 B
    case ({en,a}) // synopsys full_case6 A9 |6 ?3 b4 E5 u0 j
    3'b1_00: y[a] = 1'b1;
    5 U6 d& _& i3 r- @, s3'b1_01: y[a] = 1'b1;
      H# b' G0 e* v  @3'b1_10: y[a] = 1'b1;3 k+ ?+ H% [4 U, |/ |- ?( X
    3'b1_11: y[a] = 1'b1;
    , F$ P: ]7 j4 {1 ], Oendcase
    % y% h% S4 V- `) ?! cend2 O/ X9 z; G) \0 T  ]) X; I$ O! n
    endmodule
    $ t, R8 n8 ]7 e+ i7 w, D) RExample 13 - Decoder example with "full_case" directive
    5 R# R. }- C- I* aWarning: You are using the full_case directive with a case statement in which+ h# p) e! j( \" y7 X( B
    not all cases are covered
    / q1 Z+ H. N4 E2 Q" d, ?Statistics for case statements in always block at line 10 in file
    + z' v/ c% W$ z; |0 H9 K'.../code4b.v'" ?7 H' k- _! ]7 Q( i  s
    ===============================================
    ; m* [. ~# \0 b$ V' [! O; Z| Line | full/ parallel |
    . b& k: d7 V3 N5 _3 l) G; C' O# v===============================================
    1 E0 m" e2 e! S& l| 13 | user/auto |2 E9 }. ?4 S( D
    ===============================================% p0 S6 E0 s& H" ]
    Figure 20 - Case statement report for Example 134 N4 ^) V, s9 G% n
    + j) y4 N1 V1 t) f  t$ e
    谁给解释一下原因呢?2 s4 x$ \& T& \
    为啥会有差异?
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