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对这段文字描述感觉有些困惑

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    对这段文字描述感觉有些困惑' r! E8 ]+ q9 H4 e. s  o' r
    1 r" x) {5 B1 C1 C: q3 Z

    0 s/ ?4 [$ l, M, `1 r$ C3 g8.0 Actual "full_case" design problem: u. f8 f' N" w- [% Q
    The 2-to-4 decoder with enable in Example 12, uses a case statement that is coded without using) W# N5 X0 [7 ]8 u- X* m" C% l
    any synthesis directives. The resultant design was a decoder built from 3-input and gates and
    ) t, n' N4 ~* H$ k3 \) cinverters. No latch is inferred because all outputs are given a default assignment before the case
    6 r+ W( E- u9 O8 ~statement. For this example, the pre-synthesis and post-synthesis designs and simulations7 Q% f. }8 t$ C  j  L2 A
    matched. The 2-to-4 decoder with enable in Example 13, uses a case statement with the
    4 {- `. b6 U& g1 I$ w4 C"full_case" synthesis directive. Because of this synthesis directive, the enable input (en) was
    . H  M8 l9 R8 H" z, t4 s  s2 O; Foptimized away during synthesis and left as a dangling input. The pre-synthesis simulation
    2 K# e3 f6 C* E6 Fresults of modules code4a and code4b matched the post-synthesis simulation results of module: B5 p5 _5 e, L% \
    code4a, but did not match the post-synthesis simulation results of module code4b [2].
    " ~- L$ {0 S8 u0 K  o// no full_case
    ; E) Q/ v8 h9 s# Z// Decoder built from four 3-input and gates
    ' y' Q0 E! N4 M4 Q+ }# I// and two inverters
    7 ?% b2 j  Q- p" S: j4 Y" R. Emodule code4a (y, a, en);, U5 g% I$ L6 p' Q1 J7 ]
    output [3:0] y;
    0 \6 [* k! {5 L' X' Sinput [1:0] a;
    2 h/ p8 }  P( W: sinput en;
    & f0 Z( m% c7 L$ _! X. I5 |reg [3:0] y;
    " F2 l$ g8 U4 y  O& Z2 {always @(a or en) begin
    , `2 r6 q8 j" a  |y = 4'h0;1 d' U2 K4 D$ h
    case ({en,a})  G8 V; Y- O: ^, j
    3'b1_00: y[a] = 1'b1;
    # t( m+ m/ z8 Z9 b; p# m' E8 I8 \3'b1_01: y[a] = 1'b1;
    ; |) v8 Q0 ]" n& y5 r# S  A3 D3'b1_10: y[a] = 1'b1;
    * I" t) q# U5 P0 `+ q' @, g/ L6 n3'b1_11: y[a] = 1'b1;
      R3 Y( C: ^  [( ^* L4 u1 z" p* kendcase
    8 P# ]& e, h  r9 c# A2 Dend% z9 v6 S0 k, a5 g: C) F
    endmodule
    / t' z; b& |9 {; DExample 12 - Decoder example with no "full_case" directive. M$ u/ _& c* Y% A9 w7 R
    Statistics for case statements in always block at line 9 in file; o- {. q$ w2 Q- x4 K' w
    '.../code4a.v'/ ?6 E' Q( d# ~
    ===============================================; d; L: d8 d3 d  U* e) ?" R8 z
    | Line | full/ parallel |  }8 U6 ]! I; \0 s, h1 k
    ===============================================# D* B) {4 ?* ^3 |' e% f+ T$ Z
    | 12 | no/auto |
    * F8 i6 t* k) Z0 H4 O===============================================
    9 _; J/ g" f) ^- j! A0 C* d! pFigure 19 - Case statement report for Example 12' ]" k* c) C1 @+ H6 x( l

    " }- _! ]* Y2 }) |3 p! s; c) X8 o; V& y6 u6 z/ C: b
    // full_case example( |/ w  S" I, T5 ~5 [. ^
    // Decoder built from four 2-input nor gates  n! S/ a. W- O# L9 x
    // and two inverters) t/ Y5 c. G* t
    // The enable input is dangling (has been optimized away)
    7 @+ N& O4 K3 A8 x* e. Z  Vmodule code4b (y, a, en);* Q( ^6 ]# B. T. u5 a, \
    output [3:0] y;) ?' I/ Z, D# G8 _; i# _$ {4 Z
    input [1:0] a;
      U% T! @: A" p! }6 z8 binput en;- u' Y( u" S, S( d
    reg [3:0] y;
    ( F! f% f$ n+ L7 v% Z/ ?always @(a or en) begin) i! E: V0 Y( N% l  U' g
    y = 4'h0;
    0 q0 r; h7 }5 Bcase ({en,a}) // synopsys full_case7 }- X9 z. J' e
    3'b1_00: y[a] = 1'b1;/ ?9 K! K. A2 ~* U1 Q) o
    3'b1_01: y[a] = 1'b1;0 ^, D2 c9 m0 a2 }! n
    3'b1_10: y[a] = 1'b1;. y' b% A1 \1 a& w6 @
    3'b1_11: y[a] = 1'b1;
    + T$ [, i& l8 V. Yendcase6 p# U! a- [' n# [- j# i
    end
    9 y/ i1 H1 j" p3 qendmodule
    1 |4 E4 ~/ M3 P: x5 i$ X% A5 ]Example 13 - Decoder example with "full_case" directive+ [$ {( T" P  e+ i( v- w6 B3 K
    Warning: You are using the full_case directive with a case statement in which
    . d, l2 I/ z2 h. nnot all cases are covered9 f1 i9 J# ~& v0 E
    Statistics for case statements in always block at line 10 in file/ ]/ y4 G) }' S5 P, ]: y
    '.../code4b.v'
    ) n& E' S6 A" W! N===============================================
    ! Y& v5 z4 ^, j2 {/ N6 u( {# e- s% \7 P| Line | full/ parallel |% t) X3 U* g  V7 W. _- G
    ===============================================
    6 w7 r% f* @& s- M1 N/ D7 }| 13 | user/auto |  K) n9 C: ^: n* |: e& V
    ===============================================; x: k9 D' W8 H5 m
    Figure 20 - Case statement report for Example 134 B8 d/ N4 N4 g. K) t: B
    6 C" M4 _- i+ t- e5 Q- F
    谁给解释一下原因呢?
    ( h/ A% g% T5 H6 f/ K% [为啥会有差异?
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