对这段文字描述感觉有些困惑

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对这段文字描述感觉有些困惑
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8.0 Actual "full_case" design problem
( \8 _/ }  _6 m: \6 P, PThe 2-to-4 decoder with enable in Example 12, uses a case statement that is coded without using
any synthesis directives. The resultant design was a decoder built from 3-input and gates and
1 l' v1 Z; r( q* o; e' f7 kinverters. No latch is inferred because all outputs are given a default assignment before the case
' a: B' A# J; j+ O, W/ ^statement. For this example, the pre-synthesis and post-synthesis designs and simulations
+ @/ V& r" X7 _6 V# ^2 S! {matched. The 2-to-4 decoder with enable in Example 13, uses a case statement with the
# N: G6 X, }' Q5 |; u5 C0 ]"full_case" synthesis directive. Because of this synthesis directive, the enable input (en) was
optimized away during synthesis and left as a dangling input. The pre-synthesis simulation
results of modules code4a and code4b matched the post-synthesis simulation results of module
1 o6 y; d9 [6 V* p- Y+ Ccode4a, but did not match the post-synthesis simulation results of module code4b [2].
' W' \( N# Z0 ?2 T! P- x// no full_case
// Decoder built from four 3-input and gates
// and two inverters
module code4a (y, a, en);
output [3:0] y;
6 i2 V: i. W0 f, X5 W" Ainput [1:0] a;
input en;
reg [3:0] y;
6 _+ R6 t1 ^% |2 e, `always @(a or en) begin
y = 4'h0;
case ({en,a})
! n4 p/ w5 |; W" u) k3'b1_00: y[a] = 1'b1;
3'b1_01: y[a] = 1'b1;
3'b1_10: y[a] = 1'b1;
3'b1_11: y[a] = 1'b1;
' s3 o( R% `6 Q0 Nendcase
end
endmodule
Example 12 - Decoder example with no "full_case" directive
Statistics for case statements in always block at line 9 in file
( d- t8 u. S$ |, `# S'.../code4a.v'
' [. b( R0 o1 a$ x===============================================
| Line | full/ parallel |
1 }8 N: ]  h) P2 Z7 Z; a9 N===============================================
  \4 x8 ~' a- p| 12 | no/auto |
6 u$ y# I( s0 W===============================================
* `7 Q% O0 ?: zFigure 19 - Case statement report for Example 12

/ |% I' B. i- ]) `+ u& t4 f
; F. _  ?! F2 m6 Y0 R( f// full_case example
. N' ^! c. F! g/ V$ d  q. Y! _, h// Decoder built from four 2-input nor gates
// and two inverters
// The enable input is dangling (has been optimized away)
6 J3 Y6 ^2 e! v: ~# }& Nmodule code4b (y, a, en);
+ B* ]2 c( ~/ e9 f$ d8 v" J1 Foutput [3:0] y;
0 m3 G$ M" I% j& e  A$ jinput [1:0] a;
input en;
5 G/ c7 z/ Y8 r  i/ I/ N8 S+ ~' u( wreg [3:0] y;
always @(a or en) begin
y = 4'h0;
case ({en,a}) // synopsys full_case
" S! v2 b1 F0 X- B3'b1_00: y[a] = 1'b1;
. E! k3 w# E. i' V3'b1_01: y[a] = 1'b1;
" _4 p: V( ^" S7 T6 l! @2 b3'b1_10: y[a] = 1'b1;
& a& @/ P/ F9 r2 i7 U# g3'b1_11: y[a] = 1'b1;
3 n, B) z3 k$ i  w! c2 [7 Zendcase
end
endmodule
Example 13 - Decoder example with "full_case" directive
( e" L! G' S( E0 b6 c9 d5 GWarning: You are using the full_case directive with a case statement in which
* h" k% _7 p& |& @) z* knot all cases are covered
Statistics for case statements in always block at line 10 in file
'.../code4b.v'
===============================================
" @4 x4 B* d' J- K9 J| Line | full/ parallel |
4 B: _: C: s: _===============================================
' a+ H7 d3 d3 z4 X. R| 13 | user/auto |
: A" s2 _: B' x- W- O- O* h===============================================
Figure 20 - Case statement report for Example 13

2 j7 ^% s+ |2 o( k谁给解释一下原因呢?
! d; B/ Q+ X5 X8 G为啥会有差异?