对这段文字描述感觉有些困惑

mengzhuhao

对这段文字描述感觉有些困惑


1 x5 u! ~5 @/ ^& _$ m' X8.0 Actual "full_case" design problem
. D1 i; E) o7 Q6 S4 Q2 i- q# NThe 2-to-4 decoder with enable in Example 12, uses a case statement that is coded without using
any synthesis directives. The resultant design was a decoder built from 3-input and gates and
inverters. No latch is inferred because all outputs are given a default assignment before the case
statement. For this example, the pre-synthesis and post-synthesis designs and simulations
matched. The 2-to-4 decoder with enable in Example 13, uses a case statement with the
"full_case" synthesis directive. Because of this synthesis directive, the enable input (en) was
+ K( }' @0 J+ o+ S) B7 I- [1 X6 toptimized away during synthesis and left as a dangling input. The pre-synthesis simulation
results of modules code4a and code4b matched the post-synthesis simulation results of module
code4a, but did not match the post-synthesis simulation results of module code4b [2].
8 {. a' T6 U. C( |4 S. A/ c1 F  Z* N, h// no full_case
// Decoder built from four 3-input and gates
4 S) a- _" c& v( v8 t// and two inverters
module code4a (y, a, en);
output [3:0] y;
8 W- w0 l/ ?; l  Ainput [1:0] a;
! N+ A: m: z. I, q/ Winput en;
. U# |+ T, I1 Nreg [3:0] y;
always @(a or en) begin
7 T% _- @% D7 d8 L9 G! Xy = 4'h0;
! D/ H3 w; s+ u/ j7 Rcase ({en,a})
- A  z! B5 e& G% G2 r  T3'b1_00: y[a] = 1'b1;
1 z4 ~+ B5 a2 n+ \+ {. \+ k+ C3'b1_01: y[a] = 1'b1;
+ T& B3 H8 }- U! T) T3'b1_10: y[a] = 1'b1;
2 y7 l4 F% |* u: \3'b1_11: y[a] = 1'b1;
endcase
  l! w( f. I% Dend
+ Y* M; ?) s0 O# }5 p# Gendmodule
Example 12 - Decoder example with no "full_case" directive
) T9 G/ }( i- NStatistics for case statements in always block at line 9 in file
'.../code4a.v'
===============================================
| Line | full/ parallel |
) l# B1 q# o$ a===============================================
2 V( Y7 T6 ?9 `9 O* `& ~/ s| 12 | no/auto |
, {" q! @6 J3 ~9 R8 c$ N===============================================
$ y& U: H0 P' J( VFigure 19 - Case statement report for Example 12


// full_case example
+ a" h' c0 s3 w7 J- O( c1 A// Decoder built from four 2-input nor gates
// and two inverters
+ W& p3 a% @/ W  L  q- X// The enable input is dangling (has been optimized away)
module code4b (y, a, en);
output [3:0] y;
input [1:0] a;
input en;
reg [3:0] y;
$ B' k9 H5 S& \& w5 N8 Ualways @(a or en) begin
y = 4'h0;
8 Z4 h) o2 C1 p4 l! g- F  Y* Q3 h- R9 E$ scase ({en,a}) // synopsys full_case
* U$ C5 \% P8 x2 K; m( E' G+ x: f3'b1_00: y[a] = 1'b1;
+ G& k) _1 N0 }2 Z; U; R9 F3'b1_01: y[a] = 1'b1;
% a( j/ v- S4 p, m$ V3'b1_10: y[a] = 1'b1;
1 X, `% X( p: R) W: E3'b1_11: y[a] = 1'b1;
endcase
end
; g4 N* r" f4 |8 H5 A3 Uendmodule
Example 13 - Decoder example with "full_case" directive
6 }- w% X) z+ |5 YWarning: You are using the full_case directive with a case statement in which
not all cases are covered
7 t; O+ H2 T/ j# bStatistics for case statements in always block at line 10 in file
& K/ J6 o/ H5 _; ]# H" B'.../code4b.v'
===============================================
| Line | full/ parallel |
$ c$ m3 z2 G, Q+ @( c===============================================
. K) L+ D9 L4 s| 13 | user/auto |
===============================================
. W- O* s" G" |& ?' n3 SFigure 20 - Case statement report for Example 13
7 Y' o$ X2 H  a$ {/ b
: J  l2 x4 Z: M2 J6 M谁给解释一下原因呢?
为啥会有差异?