对这段文字描述感觉有些困惑

mengzhuhao

对这段文字描述感觉有些困惑
  c# q$ S" _" ]5 d

8.0 Actual "full_case" design problem
The 2-to-4 decoder with enable in Example 12, uses a case statement that is coded without using
any synthesis directives. The resultant design was a decoder built from 3-input and gates and
inverters. No latch is inferred because all outputs are given a default assignment before the case
; x' N9 |8 j5 P9 ~statement. For this example, the pre-synthesis and post-synthesis designs and simulations
matched. The 2-to-4 decoder with enable in Example 13, uses a case statement with the
- T# J3 ^/ V1 R  P( h4 D% c"full_case" synthesis directive. Because of this synthesis directive, the enable input (en) was
optimized away during synthesis and left as a dangling input. The pre-synthesis simulation
results of modules code4a and code4b matched the post-synthesis simulation results of module
/ T% ~4 a0 Q0 L* k0 bcode4a, but did not match the post-synthesis simulation results of module code4b [2].
// no full_case
% |( Z) `8 [  S// Decoder built from four 3-input and gates
// and two inverters
. j0 a7 w9 E6 F9 F) Qmodule code4a (y, a, en);
output [3:0] y;
input [1:0] a;
input en;
* `. |5 q8 A& ~" e$ F/ q9 Areg [3:0] y;
always @(a or en) begin
y = 4'h0;
case ({en,a})
, q) F# X5 t7 N1 n2 P+ j2 E3'b1_00: y[a] = 1'b1;
3'b1_01: y[a] = 1'b1;
8 P4 n+ l, ^, N0 H6 }3'b1_10: y[a] = 1'b1;
7 I3 ~6 G7 E) H- w' ^3'b1_11: y[a] = 1'b1;
+ B9 [  |, X) n# ]$ c( d9 T3 hendcase
+ U- p3 [4 |( u' \- ]+ S9 fend
+ n: _- {' x2 t2 @endmodule
# k3 h7 z, [; u, }6 r1 K3 O- `% gExample 12 - Decoder example with no "full_case" directive
8 S( x7 j- E* p- gStatistics for case statements in always block at line 9 in file
'.../code4a.v'
: s0 d, V/ I, j===============================================
| Line | full/ parallel |
4 o2 S6 ~; b) d3 @  i( Z3 m===============================================
% C3 k2 S# n  k6 U! r! Z8 a6 e+ k| 12 | no/auto |
  g' s; M, e9 l2 p9 q2 f9 N% ?===============================================
Figure 19 - Case statement report for Example 12

( G% K, g7 w9 n! o
( {/ T2 S! N; n# t1 D+ S0 H// full_case example
/ c. r9 X5 a+ D& d, k. r3 N// Decoder built from four 2-input nor gates
// and two inverters
; K; ~+ H& ]1 B8 {. l, R// The enable input is dangling (has been optimized away)
1 ^/ Q3 L" s; }, I! r, q. ]# {module code4b (y, a, en);
output [3:0] y;
input [1:0] a;
input en;
7 q6 [) z- G7 S3 @- |5 ?reg [3:0] y;
always @(a or en) begin
y = 4'h0;
case ({en,a}) // synopsys full_case
3'b1_00: y[a] = 1'b1;
3'b1_01: y[a] = 1'b1;
6 t0 w6 m) @, C; ]3'b1_10: y[a] = 1'b1;
3'b1_11: y[a] = 1'b1;
endcase
3 L& q2 W% i- I3 ^: B1 Cend
1 L# y; c' Z7 s3 Nendmodule
. w. R& }6 ?1 Y, CExample 13 - Decoder example with "full_case" directive
4 P* K, a' }- f, B: [Warning: You are using the full_case directive with a case statement in which
2 K3 L5 h1 P  G9 Anot all cases are covered
9 t6 @0 s1 H1 h+ R  UStatistics for case statements in always block at line 10 in file
* P5 r$ {- A/ M3 d'.../code4b.v'
4 K) K! h5 Z0 M: g3 ?( [2 l; ]===============================================
. g6 c; p. F1 o- K| Line | full/ parallel |
/ w1 \* }6 L) Q5 {+ Y; R===============================================
| 13 | user/auto |
===============================================
+ [" B  j( A; [/ S" \Figure 20 - Case statement report for Example 13
* R& d9 n! ^0 B5 O1 k, E. ^. F' G: c
谁给解释一下原因呢?
$ q# O) e& ~! Q2 L5 k为啥会有差异?