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对这段文字描述感觉有些困惑

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    对这段文字描述感觉有些困惑3 u* {" U+ C6 N$ u

    , k' v2 ~( z* @) |  @8 x( u
    * B3 s5 N- s- H6 y9 C  ^* [) w( @& {8.0 Actual "full_case" design problem
    ' v# o( C5 _  k/ o8 `  mThe 2-to-4 decoder with enable in Example 12, uses a case statement that is coded without using
    4 e  F4 F$ E& k/ o+ Jany synthesis directives. The resultant design was a decoder built from 3-input and gates and
    8 X, n/ c* G3 o8 o# ~7 w& tinverters. No latch is inferred because all outputs are given a default assignment before the case5 x# P* r" ~: @
    statement. For this example, the pre-synthesis and post-synthesis designs and simulations3 ~: q& L7 f% S/ L5 M
    matched. The 2-to-4 decoder with enable in Example 13, uses a case statement with the
    * g2 q, L! D, S/ M' I" K; x"full_case" synthesis directive. Because of this synthesis directive, the enable input (en) was& h+ |6 i! ?7 W' L9 P9 }0 g- S
    optimized away during synthesis and left as a dangling input. The pre-synthesis simulation3 R( I" L0 l2 A' A
    results of modules code4a and code4b matched the post-synthesis simulation results of module8 y8 ?4 V) {' D) A$ |) w9 I
    code4a, but did not match the post-synthesis simulation results of module code4b [2].! E' ^, {& D6 q2 c
    // no full_case
    $ m" J; _) z1 Z7 K2 g' l// Decoder built from four 3-input and gates
    + M! h( |' T1 d// and two inverters
    6 }0 U6 f+ U/ Qmodule code4a (y, a, en);
    : w2 t7 o+ l; A) q) I! B8 B3 Ioutput [3:0] y;/ K* _/ }1 |8 ]% u7 i
    input [1:0] a;
    ' h; k  Q1 s! V4 S% I+ Z& uinput en;
    ) E7 s5 a2 r4 K5 Preg [3:0] y;6 G' ^8 i4 {7 s& _3 E
    always @(a or en) begin
    5 z% ?; ]- D) v+ M8 Qy = 4'h0;
    " d, C9 o% p1 B. C2 K4 Q+ z. Mcase ({en,a})0 ^7 Y2 E5 `: S
    3'b1_00: y[a] = 1'b1;
    3 ?7 P1 U, [$ ^" ^3'b1_01: y[a] = 1'b1;1 y  [* y- I% R! H  h* O' j9 H
    3'b1_10: y[a] = 1'b1;# O* z: Q7 C. k; K1 X; O0 k
    3'b1_11: y[a] = 1'b1;8 {9 _8 b  {" @3 G2 N
    endcase
    " j" M' |, R. p) Y  [end8 Q* e9 ^" k5 v
    endmodule
    " G. L( `  X* l2 @Example 12 - Decoder example with no "full_case" directive% E9 Z8 c8 s, l3 R
    Statistics for case statements in always block at line 9 in file. f% ]% g# F) F/ d' K1 n
    '.../code4a.v'
    6 D2 C7 Q/ a  ]4 d9 h4 x  s2 E===============================================6 Z! D2 K; z6 B3 Z  g- a
    | Line | full/ parallel |
    1 w" r3 C8 x6 B. e/ a. u6 X===============================================7 R! o5 X" ]( ~5 ~' ^
    | 12 | no/auto |5 @4 O+ l2 N$ ~" ^
    ===============================================( N' v, J# E) S* P6 J/ ^) S
    Figure 19 - Case statement report for Example 12) l  a0 W9 m0 X* e( G+ b

    $ x9 u' G$ H0 G/ s* W; I1 }
    + K9 W! |" [8 g/ L8 u" ]// full_case example/ M# Y; T) Q: \5 R# L
    // Decoder built from four 2-input nor gates: K. @1 ~9 V" x/ H8 Y
    // and two inverters
    : o" Y6 b( ?+ \. s$ V5 Y// The enable input is dangling (has been optimized away). g1 z  z1 g1 C4 F
    module code4b (y, a, en);
    6 j% f. K( s% N' Poutput [3:0] y;% B+ ~4 ~, O2 e3 D/ |
    input [1:0] a;
    3 C7 i& b, x2 q4 y) H4 Qinput en;9 Q: f* m7 C+ N! A. s
    reg [3:0] y;
    ; S6 {& Z6 e: j" ?9 Nalways @(a or en) begin0 [% J% m3 K4 J7 E' R" C$ u1 Q# b. H
    y = 4'h0;
    4 Z  h/ R8 \1 ~0 ^) H5 X6 Z6 S" ?case ({en,a}) // synopsys full_case
      i# H  [) ?: U8 z8 d3'b1_00: y[a] = 1'b1;
    , m7 l6 g' g& m5 g& _$ U3'b1_01: y[a] = 1'b1;
    , {7 W% s4 q/ R' {, u4 K3'b1_10: y[a] = 1'b1;8 F: B7 D" d9 a. s5 k5 k
    3'b1_11: y[a] = 1'b1;0 W" v7 F$ f' ~
    endcase! U- M3 ^/ h8 J- h# p
    end
    ! |" K9 |- X. D  w& Mendmodule1 D8 c: a* M( g" j
    Example 13 - Decoder example with "full_case" directive6 c5 |( H" k5 u4 H4 H
    Warning: You are using the full_case directive with a case statement in which
    2 l9 @( C9 @# C$ K6 C& x' U0 E7 Z7 X; H1 Enot all cases are covered  R  B0 G2 E1 q0 c0 N5 t% D
    Statistics for case statements in always block at line 10 in file+ ^0 X1 p2 B" e  `+ `
    '.../code4b.v'. U3 s! P' n9 g
    ===============================================: {  @$ T- ?9 r' W  U& p) ]" ]
    | Line | full/ parallel |# r) E0 G5 D7 }
    ===============================================# L5 U# ]2 S( u5 `" _
    | 13 | user/auto |
    8 m( z1 K  ]0 b) o$ w1 D===============================================
    ; ?  f% C' s7 T& H$ w& hFigure 20 - Case statement report for Example 13
    ( ]" ]0 m8 ~* W7 U' ~4 ~% B; S+ \3 l( g1 D& R
    谁给解释一下原因呢?
      P$ C/ E: f' ]为啥会有差异?
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