对这段文字描述感觉有些困惑

mengzhuhao

对这段文字描述感觉有些困惑
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8.0 Actual "full_case" design problem
- ^& H5 |) e1 K  cThe 2-to-4 decoder with enable in Example 12, uses a case statement that is coded without using
, E# T) s6 [& W/ U, {; U; B/ b4 Oany synthesis directives. The resultant design was a decoder built from 3-input and gates and
. J6 J3 v& }3 J; f" vinverters. No latch is inferred because all outputs are given a default assignment before the case
6 M9 h* [& G; W! r0 x+ P" |statement. For this example, the pre-synthesis and post-synthesis designs and simulations
  y# U4 a$ n( x4 l' Dmatched. The 2-to-4 decoder with enable in Example 13, uses a case statement with the
"full_case" synthesis directive. Because of this synthesis directive, the enable input (en) was
# ~7 M- P! S$ S3 s3 J9 T$ C/ Doptimized away during synthesis and left as a dangling input. The pre-synthesis simulation
results of modules code4a and code4b matched the post-synthesis simulation results of module
5 C. W# m! |4 ?- A) ucode4a, but did not match the post-synthesis simulation results of module code4b [2].
// no full_case
// Decoder built from four 3-input and gates
// and two inverters
module code4a (y, a, en);
output [3:0] y;
input [1:0] a;
input en;
0 e! R8 u3 b- h5 @9 G" oreg [3:0] y;
always @(a or en) begin
y = 4'h0;
% o7 I% f# u  A+ J8 J4 I9 `. ~8 jcase ({en,a})
8 p7 S( X7 S6 |, u; E3 B3'b1_00: y[a] = 1'b1;
: \$ W% P: o% }3'b1_01: y[a] = 1'b1;
3'b1_10: y[a] = 1'b1;
8 F1 v7 k: d1 l3'b1_11: y[a] = 1'b1;
4 }  \/ t; a: lendcase
& N3 T: I) ]: p% K4 Y# i9 J! k7 Vend
endmodule
4 Z, m/ a: F$ D/ R; \4 TExample 12 - Decoder example with no "full_case" directive
Statistics for case statements in always block at line 9 in file
'.../code4a.v'
===============================================
| Line | full/ parallel |
===============================================
2 ?1 N0 @5 X3 @4 Z- C| 12 | no/auto |
===============================================
Figure 19 - Case statement report for Example 12


// full_case example
& S3 u/ _( j* t. u# ^// Decoder built from four 2-input nor gates
) b% N* j* C! ]- D// and two inverters
// The enable input is dangling (has been optimized away)
: h8 Y4 ~( d$ g2 ^) a7 |6 L2 f4 a' pmodule code4b (y, a, en);
output [3:0] y;
input [1:0] a;
input en;
reg [3:0] y;
9 w4 H% O; W7 _/ D6 Malways @(a or en) begin
y = 4'h0;
/ {! T2 h- b1 Y+ ~+ vcase ({en,a}) // synopsys full_case
3'b1_00: y[a] = 1'b1;
9 W$ ^1 t0 m8 I+ Z4 V# V! R8 |3'b1_01: y[a] = 1'b1;
3'b1_10: y[a] = 1'b1;
3'b1_11: y[a] = 1'b1;
- C* d9 E' w+ B+ D7 j8 a) v2 u  Q3 G/ Eendcase
; Q4 ~: o; U2 p6 o! R$ V% }end
endmodule
Example 13 - Decoder example with "full_case" directive
Warning: You are using the full_case directive with a case statement in which
) P8 D3 ~$ W' fnot all cases are covered
Statistics for case statements in always block at line 10 in file
6 w% C3 G6 ?& u, B8 |0 t% l'.../code4b.v'
" M4 w! v& G6 l9 o0 F' `===============================================
| Line | full/ parallel |
===============================================
7 t7 A1 j9 h& c' H: |+ [, ~) g) \6 Z| 13 | user/auto |
6 |. _6 U0 v1 g===============================================
$ D  s2 [% M  T  KFigure 20 - Case statement report for Example 13

谁给解释一下原因呢?
为啥会有差异?