TA的每日心情 | 擦汗 2020-1-14 15:59 |
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对这段文字描述感觉有些困惑( L* o0 o' m2 Y2 r9 p
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1 x5 u! ~5 @/ ^& _$ m' X8.0 Actual "full_case" design problem
. D1 i; E) o7 Q6 S4 Q2 i- q# NThe 2-to-4 decoder with enable in Example 12, uses a case statement that is coded without using) f$ W% [. t8 o) d+ s" C
any synthesis directives. The resultant design was a decoder built from 3-input and gates and8 a/ x. T( f5 g& a
inverters. No latch is inferred because all outputs are given a default assignment before the case* l* I, K' l! d* X" x: e
statement. For this example, the pre-synthesis and post-synthesis designs and simulations( X5 l3 {7 ?) P' s" o/ z
matched. The 2-to-4 decoder with enable in Example 13, uses a case statement with the$ g8 G" K" j! T- s$ ?
"full_case" synthesis directive. Because of this synthesis directive, the enable input (en) was
+ K( }' @0 J+ o+ S) B7 I- [1 X6 toptimized away during synthesis and left as a dangling input. The pre-synthesis simulation1 W/ H' S7 ~) B
results of modules code4a and code4b matched the post-synthesis simulation results of module! }. ~$ e9 Y* ]! M9 r/ l0 t) w
code4a, but did not match the post-synthesis simulation results of module code4b [2].
8 {. a' T6 U. C( |4 S. A/ c1 F Z* N, h// no full_case* U! t3 \$ C, f4 F$ F! H" o! k
// Decoder built from four 3-input and gates
4 S) a- _" c& v( v8 t// and two inverters0 g) m8 d: P$ ~- ]" P
module code4a (y, a, en);0 o8 v1 Q; _% O. |
output [3:0] y;
8 W- w0 l/ ?; l Ainput [1:0] a;
! N+ A: m: z. I, q/ Winput en;
. U# |+ T, I1 Nreg [3:0] y; J, k' Y. N$ \% p. y2 ?0 ?- M& `3 n
always @(a or en) begin
7 T% _- @% D7 d8 L9 G! Xy = 4'h0;
! D/ H3 w; s+ u/ j7 Rcase ({en,a})
- A z! B5 e& G% G2 r T3'b1_00: y[a] = 1'b1;
1 z4 ~+ B5 a2 n+ \+ {. \+ k+ C3'b1_01: y[a] = 1'b1;
+ T& B3 H8 }- U! T) T3'b1_10: y[a] = 1'b1;
2 y7 l4 F% |* u: \3'b1_11: y[a] = 1'b1;% P: A! u& V( \1 d
endcase
l! w( f. I% Dend
+ Y* M; ?) s0 O# }5 p# Gendmodule. b( P3 ?- P% w$ ?# n4 {' b
Example 12 - Decoder example with no "full_case" directive
) T9 G/ }( i- NStatistics for case statements in always block at line 9 in file% h# ?6 V/ M5 w t
'.../code4a.v'4 b% X: V: B9 A( J( _; Y# o
===============================================+ I& z5 ~9 Q6 V0 ]/ B
| Line | full/ parallel |
) l# B1 q# o$ a===============================================
2 V( Y7 T6 ?9 `9 O* `& ~/ s| 12 | no/auto |
, {" q! @6 J3 ~9 R8 c$ N===============================================
$ y& U: H0 P' J( VFigure 19 - Case statement report for Example 12' l# v: ?" e9 N, f& c
5 i7 m- z+ ?2 C, n
: [3 ` d ^9 H F0 Q" y9 P* w
// full_case example
+ a" h' c0 s3 w7 J- O( c1 A// Decoder built from four 2-input nor gates) G1 ^! U0 O& F n. I1 y m& s- J
// and two inverters
+ W& p3 a% @/ W L q- X// The enable input is dangling (has been optimized away)/ B+ @) T' ~; |1 p
module code4b (y, a, en);# n' r3 k' Z* H
output [3:0] y;2 e9 ?- L8 x7 O( I/ ~5 W
input [1:0] a;5 H! `! s1 D3 }8 g
input en;$ d o1 ~0 t f' A; R
reg [3:0] y;
$ B' k9 H5 S& \& w5 N8 Ualways @(a or en) begin/ \( ~3 [7 z) u& O" H( w3 I
y = 4'h0;
8 Z4 h) o2 C1 p4 l! g- F Y* Q3 h- R9 E$ scase ({en,a}) // synopsys full_case
* U$ C5 \% P8 x2 K; m( E' G+ x: f3'b1_00: y[a] = 1'b1;
+ G& k) _1 N0 }2 Z; U; R9 F3'b1_01: y[a] = 1'b1;
% a( j/ v- S4 p, m$ V3'b1_10: y[a] = 1'b1;
1 X, `% X( p: R) W: E3'b1_11: y[a] = 1'b1;! T) r1 j* q; g/ D# {5 a
endcase* E/ Y- F3 z8 z* H+ t
end
; g4 N* r" f4 |8 H5 A3 Uendmodule6 H w6 [- S6 X( ?
Example 13 - Decoder example with "full_case" directive
6 }- w% X) z+ |5 YWarning: You are using the full_case directive with a case statement in which" [9 @% @6 v0 c/ L
not all cases are covered
7 t; O+ H2 T/ j# bStatistics for case statements in always block at line 10 in file
& K/ J6 o/ H5 _; ]# H" B'.../code4b.v'- G' I) c( A: E; z# _& ^& }0 k0 s/ F
===============================================3 E+ B8 m9 x: d4 f8 O
| Line | full/ parallel |
$ c$ m3 z2 G, Q+ @( c===============================================
. K) L+ D9 L4 s| 13 | user/auto |3 `# G: i: [. d; W2 H
===============================================
. W- O* s" G" |& ?' n3 SFigure 20 - Case statement report for Example 13
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: J l2 x4 Z: M2 J6 M谁给解释一下原因呢?( B; y8 I' @6 z( L/ S8 Q/ J
为啥会有差异? |
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