对这段文字描述感觉有些困惑

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对这段文字描述感觉有些困惑

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8.0 Actual "full_case" design problem
The 2-to-4 decoder with enable in Example 12, uses a case statement that is coded without using
any synthesis directives. The resultant design was a decoder built from 3-input and gates and
inverters. No latch is inferred because all outputs are given a default assignment before the case
statement. For this example, the pre-synthesis and post-synthesis designs and simulations
matched. The 2-to-4 decoder with enable in Example 13, uses a case statement with the
"full_case" synthesis directive. Because of this synthesis directive, the enable input (en) was
) [; p, r2 E3 woptimized away during synthesis and left as a dangling input. The pre-synthesis simulation
  J$ j7 ^! C  }( l& j' f6 F0 ]* rresults of modules code4a and code4b matched the post-synthesis simulation results of module
code4a, but did not match the post-synthesis simulation results of module code4b [2].
// no full_case
// Decoder built from four 3-input and gates
// and two inverters
module code4a (y, a, en);
, a* w( ^' I1 C: T5 }output [3:0] y;
input [1:0] a;
input en;
reg [3:0] y;
, w" g3 }' u3 z8 T/ U: ]! Yalways @(a or en) begin
y = 4'h0;
7 T; L) o8 e/ y- Z0 R# K* h7 F8 R; Scase ({en,a})
3'b1_00: y[a] = 1'b1;
3'b1_01: y[a] = 1'b1;
/ l) K# S- u; q) J4 d3'b1_10: y[a] = 1'b1;
) \( b% H& |/ Z8 k- S9 F3'b1_11: y[a] = 1'b1;
endcase
end
endmodule
* R7 ?! e+ d1 y& f; D% NExample 12 - Decoder example with no "full_case" directive
- r! q# d& H& gStatistics for case statements in always block at line 9 in file
: [$ H0 r1 l! v3 [/ d/ v' X'.../code4a.v'
===============================================
| Line | full/ parallel |
===============================================
( [& O/ H2 Y; ~| 12 | no/auto |
===============================================
Figure 19 - Case statement report for Example 12
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// full_case example
- B/ t& S9 z6 F5 P# H- |// Decoder built from four 2-input nor gates
// and two inverters
// The enable input is dangling (has been optimized away)
module code4b (y, a, en);
- t# w, M' r, Q3 |  xoutput [3:0] y;
input [1:0] a;
input en;
reg [3:0] y;
9 a2 W6 ~9 ?. V# b# g+ }3 E! m: q# l6 Aalways @(a or en) begin
- S+ P- M, m$ k3 p. ?# W" s, Ey = 4'h0;
9 G2 r& D4 r& k4 Dcase ({en,a}) // synopsys full_case
3'b1_00: y[a] = 1'b1;
" o3 E/ Y3 T. L0 z3'b1_01: y[a] = 1'b1;
$ _5 @) u, l; Y. O/ M3'b1_10: y[a] = 1'b1;
3'b1_11: y[a] = 1'b1;
" |: I7 B+ G/ R( qendcase
end
) r0 p, S' ?) r9 \/ |" Wendmodule
3 q- J* _6 x4 n5 O) KExample 13 - Decoder example with "full_case" directive
2 [9 L% D. d% o* u# IWarning: You are using the full_case directive with a case statement in which
not all cases are covered
Statistics for case statements in always block at line 10 in file
' a" R  h5 y. N, g% i'.../code4b.v'
===============================================
| Line | full/ parallel |
===============================================
5 V, Z9 z  _1 G| 13 | user/auto |
% x) c8 g# _. M9 P, ^$ D7 b===============================================
Figure 20 - Case statement report for Example 13
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谁给解释一下原因呢?
2 g) F  O# ^4 t+ G& T1 e为啥会有差异?