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对这段文字描述感觉有些困惑

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    对这段文字描述感觉有些困惑4 ]6 ]( \. C/ R, ?  C

    % P" g5 {) z, p6 I: @3 j
    : D: L0 `, c" s+ X5 E* V# U2 O8.0 Actual "full_case" design problem" n3 K. W, Z( J+ x4 A
    The 2-to-4 decoder with enable in Example 12, uses a case statement that is coded without using. D& ]8 K! Y- t, U  I2 ]& P
    any synthesis directives. The resultant design was a decoder built from 3-input and gates and
    # b' @/ J8 `1 Z3 Q! F* Zinverters. No latch is inferred because all outputs are given a default assignment before the case4 G+ ~4 L0 X0 p
    statement. For this example, the pre-synthesis and post-synthesis designs and simulations
    $ u- T( b+ b. H- U4 ], _. Rmatched. The 2-to-4 decoder with enable in Example 13, uses a case statement with the0 {2 B. e4 O: G
    "full_case" synthesis directive. Because of this synthesis directive, the enable input (en) was
    + s5 a/ H5 P. M+ V; A# P" @$ Foptimized away during synthesis and left as a dangling input. The pre-synthesis simulation
    4 F. \- B8 Z7 ]9 ^/ L4 Eresults of modules code4a and code4b matched the post-synthesis simulation results of module! Z- Z! u3 N0 m5 |& S' p3 z* j
    code4a, but did not match the post-synthesis simulation results of module code4b [2].
    ; j" C# k' r6 `" G0 {// no full_case
    1 F& [6 n. E7 O9 F// Decoder built from four 3-input and gates
    % p+ D( k# X+ A5 g// and two inverters
    3 i% H; f' E% Z% L$ @! |module code4a (y, a, en);: ~7 k; k, f; R
    output [3:0] y;
    0 ]! _9 b: t( t9 ninput [1:0] a;
    # z# \" ?: z: {; J& dinput en;
    % g: G2 m1 @3 q; M; v  o3 H. K" @, oreg [3:0] y;. ?1 d: q. _- U6 O' [5 p5 D
    always @(a or en) begin8 ?: S1 w; P7 u# z2 F( d: a0 o% c: d
    y = 4'h0;  M2 r7 ]0 t0 ^) O$ H/ o- H7 L; p. L
    case ({en,a})
    * ~7 Q: f2 u9 a! X9 X3'b1_00: y[a] = 1'b1;+ M  n( i* f5 n" Z& j4 Y% w9 k$ y
    3'b1_01: y[a] = 1'b1;' w1 h1 t( u" j; y4 O/ L
    3'b1_10: y[a] = 1'b1;3 M/ p8 w2 ^6 N' p$ C( a/ j
    3'b1_11: y[a] = 1'b1;- i. D2 f- B1 p
    endcase. i' N. s$ ^8 p- u& m; q
    end6 q  V: w$ w& ^8 {% n, b; x
    endmodule
    $ Z' y2 a3 v. ?7 a/ r, p7 S# n7 `- OExample 12 - Decoder example with no "full_case" directive
    , [. Q" x- E# j" E" H1 ]0 \Statistics for case statements in always block at line 9 in file0 N' I6 h8 O" j' J( W' t
    '.../code4a.v'
    3 P+ o) U: \2 C2 F===============================================
    $ y: V' S, I  E8 M& {* A6 M| Line | full/ parallel |
    , v) G9 M6 E5 u% G$ j/ }6 ?===============================================+ X. V" x6 t* C
    | 12 | no/auto |
    1 H, o% ^# O5 h& R. ^===============================================; p6 j: X, G5 @+ v% C" r: ]6 q7 W5 y
    Figure 19 - Case statement report for Example 12- }7 V; l4 W7 A8 k% y5 a* p! k

      F$ q- ]4 u, @( V/ w8 M" ~1 v2 \1 R# s+ p$ E; y6 L6 o
    // full_case example
    0 s1 T# u( w" B) x' B* q6 F// Decoder built from four 2-input nor gates
    $ h2 q8 {7 P( o- G$ @6 L6 Y3 z// and two inverters
    2 H) z6 `8 Z8 u// The enable input is dangling (has been optimized away)
    3 f6 |* d& E% [& ]6 B, K: cmodule code4b (y, a, en);
    9 j1 N& s( r$ d. B& x8 @: J  M7 poutput [3:0] y;
    0 U7 z' r, X6 s6 E4 w9 o! ^input [1:0] a;/ ^* @) g+ R, l. K
    input en;6 ~: y7 E: O+ p
    reg [3:0] y;& q0 n2 d, c+ V+ ^- c0 F
    always @(a or en) begin1 m( t) Z7 ?8 y. ^5 b
    y = 4'h0;
    ! |' Q- i( P% `8 Bcase ({en,a}) // synopsys full_case
    & `  s% a- W% Q  @3'b1_00: y[a] = 1'b1;
    4 w9 S2 {8 |( {# R; T: ?( h3'b1_01: y[a] = 1'b1;
    6 T) d- \5 j- ^9 T" }; ?/ u3'b1_10: y[a] = 1'b1;" @# W" v+ K/ `; A& ^8 M( |, P' }
    3'b1_11: y[a] = 1'b1;( r7 Z0 q7 a9 Z( U+ f. u+ Q5 e
    endcase6 H, L9 }9 G0 \% r; g) ?
    end# m$ @& Z* o1 I4 X' m, {/ g
    endmodule
    ! ]& ?8 t" F6 }Example 13 - Decoder example with "full_case" directive
    . w5 e8 }8 t% LWarning: You are using the full_case directive with a case statement in which
    , T6 e- f4 c+ `) H0 P& V8 T+ Fnot all cases are covered, ]1 h; X' M) {- \1 X
    Statistics for case statements in always block at line 10 in file1 p3 g# ~  v& F  P8 t
    '.../code4b.v'
    8 j$ C+ o9 ]- V% B  I$ y& z===============================================% G) ]# v( V  `4 F9 g5 h
    | Line | full/ parallel |
    ( Z- e% d+ R% r. r" l; S9 }' V0 t===============================================& s/ C8 U4 g' s* N: j2 R
    | 13 | user/auto |, V$ j5 l. n$ W- z# @6 R
    ===============================================2 P6 N& V) U* F) I
    Figure 20 - Case statement report for Example 13
    ! k( P' E! A1 y. ?! y5 x" M( X: Z. F9 I
    谁给解释一下原因呢?
    # G2 X5 V- ~) l0 o! W为啥会有差异?
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