对这段文字描述感觉有些困惑

mengzhuhao

对这段文字描述感觉有些困惑


8 W, U. Y$ Z0 Q( C2 l& N8.0 Actual "full_case" design problem
The 2-to-4 decoder with enable in Example 12, uses a case statement that is coded without using
2 q  e: K2 a9 d1 ?9 \; b; bany synthesis directives. The resultant design was a decoder built from 3-input and gates and
: R* y3 T% L- einverters. No latch is inferred because all outputs are given a default assignment before the case
. Q7 Y% W0 u) W/ `" f; a! U5 v) Xstatement. For this example, the pre-synthesis and post-synthesis designs and simulations
matched. The 2-to-4 decoder with enable in Example 13, uses a case statement with the
: o/ g8 _0 b8 ]% V) m# y- p' W"full_case" synthesis directive. Because of this synthesis directive, the enable input (en) was
optimized away during synthesis and left as a dangling input. The pre-synthesis simulation
results of modules code4a and code4b matched the post-synthesis simulation results of module
code4a, but did not match the post-synthesis simulation results of module code4b [2].
, x( h! }# H4 r) P% [- O// no full_case
& h. `5 [. ]$ M// Decoder built from four 3-input and gates
9 P( k( {4 ?; G! h// and two inverters
module code4a (y, a, en);
. `9 e& h7 q$ Q1 soutput [3:0] y;
input [1:0] a;
input en;
' J9 I# F1 u2 Q6 oreg [3:0] y;
) d, l4 V' e) v( G$ calways @(a or en) begin
y = 4'h0;
* H: F) s8 n6 a7 h8 Xcase ({en,a})
3'b1_00: y[a] = 1'b1;
* K; d9 f, g8 V3'b1_01: y[a] = 1'b1;
7 q% g9 C% Q0 x! b& y3'b1_10: y[a] = 1'b1;
3'b1_11: y[a] = 1'b1;
endcase
# N2 n* g/ Q# w# V7 ^end
endmodule
Example 12 - Decoder example with no "full_case" directive
Statistics for case statements in always block at line 9 in file
$ R1 |# q# }- z$ l" A; f# u'.../code4a.v'
===============================================
! ~! B, v0 k- b3 K/ D& h( O9 x| Line | full/ parallel |
- x; h9 ?) l3 d& n. Y4 G$ |===============================================
! j  {4 @& ~! X. x4 [5 o| 12 | no/auto |
===============================================
( p+ ]$ [: p+ m( ^+ BFigure 19 - Case statement report for Example 12


& ^7 B9 F0 U, I6 \5 s// full_case example
4 q* S) w- z7 b  G& `9 \2 t// Decoder built from four 2-input nor gates
; k6 Q1 I( |: i+ A! F6 H// and two inverters
// The enable input is dangling (has been optimized away)
module code4b (y, a, en);
- f& O6 G) |6 z3 e# o# `  y0 Voutput [3:0] y;
! v- S: w$ P9 \5 c' \input [1:0] a;
input en;
reg [3:0] y;
5 L) {9 p" O) ralways @(a or en) begin
y = 4'h0;
. V2 C6 e2 I4 y' n2 r3 x. Ncase ({en,a}) // synopsys full_case
5 I; G! Q% _. [  E/ e; r6 Q, L3'b1_00: y[a] = 1'b1;
. }1 h( K. f/ E5 x  O  P3'b1_01: y[a] = 1'b1;
- \7 G* K  C1 k- V3'b1_10: y[a] = 1'b1;
3'b1_11: y[a] = 1'b1;
0 A  }" z/ S# g8 W# V# ?endcase
2 r! n0 g( ~, }  d  }. hend
# e( G) b% Q# X) R$ c  g2 Gendmodule
3 V' e; X! E1 b: t9 ^7 {; [/ V' bExample 13 - Decoder example with "full_case" directive
Warning: You are using the full_case directive with a case statement in which
5 }1 p* P/ h9 Enot all cases are covered
* {8 F8 z6 r- w1 rStatistics for case statements in always block at line 10 in file
'.../code4b.v'
* V' N4 v2 I  O7 G===============================================
1 P4 A) c8 }6 G) M7 Z0 x| Line | full/ parallel |
- s& D5 i! v' U" L===============================================
: j, J1 `  x4 x% c0 I| 13 | user/auto |
===============================================
+ L" N8 {- Z7 g1 LFigure 20 - Case statement report for Example 13

谁给解释一下原因呢?
为啥会有差异?