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对这段文字描述感觉有些困惑

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    对这段文字描述感觉有些困惑
    ) t+ U* Z* P: l$ d0 j
    ; h! ^2 j6 b0 c2 \# s9 d# y/ O. ], D# L- q
    8.0 Actual "full_case" design problem
    - ^& H5 |) e1 K  cThe 2-to-4 decoder with enable in Example 12, uses a case statement that is coded without using
    , E# T) s6 [& W/ U, {; U; B/ b4 Oany synthesis directives. The resultant design was a decoder built from 3-input and gates and
    . J6 J3 v& }3 J; f" vinverters. No latch is inferred because all outputs are given a default assignment before the case
    6 M9 h* [& G; W! r0 x+ P" |statement. For this example, the pre-synthesis and post-synthesis designs and simulations
      y# U4 a$ n( x4 l' Dmatched. The 2-to-4 decoder with enable in Example 13, uses a case statement with the7 o- |+ `% W- v0 F# A
    "full_case" synthesis directive. Because of this synthesis directive, the enable input (en) was
    # ~7 M- P! S$ S3 s3 J9 T$ C/ Doptimized away during synthesis and left as a dangling input. The pre-synthesis simulation, ]% P7 C! y6 E- g" m) O7 R/ i
    results of modules code4a and code4b matched the post-synthesis simulation results of module
    5 C. W# m! |4 ?- A) ucode4a, but did not match the post-synthesis simulation results of module code4b [2].7 f3 w; T4 M( M2 K/ @
    // no full_case4 H) l2 D2 m, ?. a1 A0 e
    // Decoder built from four 3-input and gates+ F5 h' |8 H5 h* f; C; S" b6 J: r$ q
    // and two inverters- p9 H3 M9 [& b' h9 D, {2 i+ r: L
    module code4a (y, a, en);& ]1 V. w3 q$ k
    output [3:0] y;8 P% \3 N7 [3 j0 g& ]
    input [1:0] a;6 U6 j4 R0 K1 g) _7 K, g% G6 w
    input en;
    0 e! R8 u3 b- h5 @9 G" oreg [3:0] y;) H5 y/ `% X( |; U2 q4 ]! t
    always @(a or en) begin. s- o/ ~% K' r( h" Q
    y = 4'h0;
    % o7 I% f# u  A+ J8 J4 I9 `. ~8 jcase ({en,a})
    8 p7 S( X7 S6 |, u; E3 B3'b1_00: y[a] = 1'b1;
    : \$ W% P: o% }3'b1_01: y[a] = 1'b1;6 G4 ]9 u. s$ Y; C2 w; A
    3'b1_10: y[a] = 1'b1;
    8 F1 v7 k: d1 l3'b1_11: y[a] = 1'b1;
    4 }  \/ t; a: lendcase
    & N3 T: I) ]: p% K4 Y# i9 J! k7 Vend* O7 C* I  B7 [/ y0 X$ b$ T+ ?( n
    endmodule
    4 Z, m/ a: F$ D/ R; \4 TExample 12 - Decoder example with no "full_case" directive6 y6 q) p! j/ U. B4 L  d# A
    Statistics for case statements in always block at line 9 in file1 S. i/ w0 z% I* S) D7 S
    '.../code4a.v'. @6 b, Y" D8 n
    ===============================================6 v" d+ F3 A( a& b. ]0 z4 e8 c
    | Line | full/ parallel |  m; }6 G. F) [+ d
    ===============================================
    2 ?1 N0 @5 X3 @4 Z- C| 12 | no/auto |2 n% g$ P. g. R+ b! \" w" q
    ===============================================3 K# T; _4 v1 u4 j) l
    Figure 19 - Case statement report for Example 12; j- j7 W9 M& ^/ J6 a0 \) ^
    & X. q5 x# y6 Y, M! h4 [
    3 e- B1 D& D2 R0 q5 Z2 V. Y: V
    // full_case example
    & S3 u/ _( j* t. u# ^// Decoder built from four 2-input nor gates
    ) b% N* j* C! ]- D// and two inverters* U! e5 y) ?- L8 N, p3 E" N
    // The enable input is dangling (has been optimized away)
    : h8 Y4 ~( d$ g2 ^) a7 |6 L2 f4 a' pmodule code4b (y, a, en);5 Y- D) N; ^7 w/ R* A2 B  m
    output [3:0] y;9 Z8 N+ Q6 T0 j& y. l7 W5 C. ^0 E. A+ \
    input [1:0] a;" ^1 z: y. i+ U! y, @6 x
    input en;6 x6 v$ g  K0 E
    reg [3:0] y;
    9 w4 H% O; W7 _/ D6 Malways @(a or en) begin: x* V0 F0 h! M5 T, ^
    y = 4'h0;
    / {! T2 h- b1 Y+ ~+ vcase ({en,a}) // synopsys full_case% }, Y6 S0 c. H( d7 Z+ c
    3'b1_00: y[a] = 1'b1;
    9 W$ ^1 t0 m8 I+ Z4 V# V! R8 |3'b1_01: y[a] = 1'b1;1 X& p; ~* P0 `4 x  `
    3'b1_10: y[a] = 1'b1;3 l( u# Z/ S% M0 G$ d
    3'b1_11: y[a] = 1'b1;
    - C* d9 E' w+ B+ D7 j8 a) v2 u  Q3 G/ Eendcase
    ; Q4 ~: o; U2 p6 o! R$ V% }end; o+ L( o* |4 X/ {! M
    endmodule: b9 h8 F% {$ ^. b' I
    Example 13 - Decoder example with "full_case" directive' ~# w4 L5 a. F; u0 a# J# w
    Warning: You are using the full_case directive with a case statement in which
    ) P8 D3 ~$ W' fnot all cases are covered, Q! T+ O+ c8 |7 N% }3 f
    Statistics for case statements in always block at line 10 in file
    6 w% C3 G6 ?& u, B8 |0 t% l'.../code4b.v'
    " M4 w! v& G6 l9 o0 F' `===============================================: S! y: }$ k4 P6 T1 d& [2 q
    | Line | full/ parallel |6 U- R5 Q% P3 u$ U0 e8 @0 ?/ i
    ===============================================
    7 t7 A1 j9 h& c' H: |+ [, ~) g) \6 Z| 13 | user/auto |
    6 |. _6 U0 v1 g===============================================
    $ D  s2 [% M  T  KFigure 20 - Case statement report for Example 133 ?2 D, ^+ C$ D
    3 W! k( R# C8 i- b. u
    谁给解释一下原因呢?* E2 s6 O. j! j
    为啥会有差异?
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