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DRC - (Final DRC)
) F- C3 U) @& o+ }1 m" ~ -----------------9 j4 u/ ?8 U5 b" O _/ j
& S2 _( a6 P+ ?. @" D% g& a
08:00 AM TuESDay, September 09, 2008
: J* R7 u. l' Z9 s- i9 ^& Q) E. u Job Name: D:\prj\080906\PCB\22V1.0.pcb3 S! t* J9 J& s5 c! G% A4 K" G
N: S( I: w! u+ ~4 s9 f4 D* H
5 K6 J' G" ?2 ~4 V ---------/ e/ W; E7 Z5 i8 W
PROXIMITY
, t. Z2 v; w. n% B$ F ---------8 t( z1 r, Y7 `7 w& J
! G/ \% ~4 M; n! s8 t
Use DRC Window : NO! U& j y @) a" `- o( h
0 U* p: ?+ K( t* y
# X+ F$ y6 G8 Q' Z& F
Disable Same Cell Pad-Pad Checks : NO
, i+ j0 H; c+ N
$ J: S# X7 C3 M! _. T
( n; n4 G* O z& [9 L$ O4 l Enable Same Net Pad-Pad Checks : NO
" H5 g9 f1 }: l- {7 m! G6 A- c# u' q
# K- O' f/ O& I, d2 I" }& F
Layers Specifed To Check : Layer 1
" ?& H9 I. |. r ~8 r Layer 2
|& \. ` C# Z" E# y; F1 ~3 a5 n q4 N' ]5 H% Y7 a
^+ N+ b t( x0 v$ C. P
1 ~* W3 {$ ]+ F. l
8 p% Z( g) W! C( r# T8 Z1 w0 W) w: f Net Class Clearances And Rules
+ n' R1 x/ _5 T( W) x& C ------------------------------
5 y! ^ `5 J) u' p7 j% E- [6 P& K
>> Components Top TO Components Top
# Q4 p* j" u# K Hazards Found : 4+ E, x1 w1 k4 ^) a9 x6 ?# @1 u
* M% q" [2 n: }
Traces Layer 1 TO Traces Layer 1
7 L6 R, ~ L8 W9 Y0 f( I1 } No Hazards.
. B5 [8 G3 ?, W2 l- b$ m% n
: c, t" u# V, F& ? D Traces Layer 1 TO Part pads SMD Layer 1
! {& w$ Q1 ~- r/ u No Hazards.' l& K# ~6 i) c) r2 t7 X
+ S+ v: e$ U7 b M Traces Layer 1 TO Part Pads Thru Layer 1, q+ V5 {4 B# ?- ]6 T
No Hazards.0 _7 l7 ?8 A- ~) d/ Q! \
/ a+ i( l; M% c Traces Layer 1 TO Part Holes Layer 1
4 b" S' y2 _" t; j3 o No Hazards.
4 E. m2 u% ?0 E& L- |- N" L7 W0 j2 R+ t5 s
Traces Layer 1 TO Via Pads Layer 17 f; \8 D8 {/ t( d
No Hazards.0 S, F8 L% L- r6 [' n
; b5 m' B# p- _* I z
Traces Layer 1 TO Via Holes Layer 1( V9 O+ V. G' z9 j$ O2 C* n# I
No Hazards.( [ x3 f" f7 `, I& s
6 S7 f& G: J4 q% N
Part Pads SMD Layer 1 TO Part Pads SMD Layer 1+ z5 U/ x9 {) J0 R' M- H, ?, U: }
No Hazards.( W) T5 ~9 p! ^0 W7 m. y
; ^9 {! G3 B) _3 D! t! l Part Pads SMD Layer 1 TO Part Pads Thru Layer 1
3 L h- G; `. l& b( w$ @; K7 D; ^ No Hazards.
" G' X& k7 f' r0 Z7 A0 b0 H
0 n' M. U* o t Part Pads SMD Layer 1 TO Part Holes Layer 1/ G) s0 t' _% _0 N# z9 E! x
No Hazards./ d* _: a s4 b
5 s h! y/ p, r! B Part Pads SMD Layer 1 TO Via Pads Layer 11 B p* [, y; P. f' q( j) f$ \8 a
No Hazards.
# k$ y+ \. D5 a5 U; B- x1 T
( w4 ]7 z# @$ N: t5 b! N0 k Part Pads SMD Layer 1 TO Via Holes Layer 1
% c& ?" b, _; p, L) l* t, H( O2 q No Hazards.6 u: K/ v# g+ D1 Y2 h& e
* S p: W0 w9 U4 V; H+ o' n% J2 F$ m Part Pads Thru Layer 1 TO Part Pads Thru Layer 1
0 q( c3 v- ?+ q No Hazards.
$ u5 |2 G; m- J
4 W7 `1 u. L6 Y7 d9 K Part Pads Thru Layer 1 TO Part Holes Layer 18 _2 a4 ]/ p% y) p" e6 e6 @
No Hazards.
7 B6 Z# @ t) \2 ?8 S; A7 H. X; t( \% ]. x
Part Pads Thru Layer 1 TO Via Pads Layer 1
* L9 i' K+ K$ l! ?% [" m No Hazards.
: O! T# S6 U8 F" q, x+ Z7 i( j/ u6 a- H# h0 t0 K; b
Part Pads Thru Layer 1 TO Via Holes Layer 18 C7 {" g1 y& v* z( c, f
No Hazards.- }7 G; x1 w6 A0 L4 b8 J' b" o
, D/ P4 A/ @, |" L Part Holes Layer 1 TO Via Pads Layer 1
. N! K8 }' R, [! @2 v: |0 i No Hazards.
; L4 `+ d9 a$ r- p, O0 t+ q+ M. ]
Part Holes Layer 1 TO Via Holes Layer 1
- }, _ y; |7 S C No Hazards./ k) ^, s' d8 Y9 e3 z7 e" y
. h6 c6 J9 M1 `- I" p) }
Via Pads Layer 1 TO Via Pads Layer 1! h7 |/ s. @% ^7 @! M# X
No Hazards.. t' j0 @4 B; B) B
$ L8 i6 ]: e- g Via Pads Layer 1 TO Via Holes Layer 1
' u) p. q" s h& o No Hazards./ O1 ?/ e: V3 s. @' r
! [! h* @9 G r, j% o Via Holes Layer 1 TO Via Holes Layer 1
1 K7 e7 `" ? N No Hazards.
4 e# Q6 |7 q' w6 N L* X% @: t; y: w9 s6 N( b4 \; Y1 q: Y5 T
Traces Layer 2 TO Traces Layer 28 o8 Q% O2 e/ b& O) o; Q# a
No Hazards.
" H8 p/ D/ S8 [. n4 d) q7 o$ @) b% m. B% `; r4 b# a
Traces Layer 2 TO Part Pads SMD Layer 2
/ x' r4 b7 c9 [$ C0 D No Hazards.' s" s5 ^' b+ y
0 s( Q0 `! }. i& U$ p( A Traces Layer 2 TO Part Pads Thru Layer 2/ {5 n3 u* X6 `7 Y( x+ j1 l
No Hazards.
% O4 ^! P2 F, v8 e) R# @ R, O9 U: b
Traces Layer 2 TO Part Holes Layer 2
0 {6 \' o9 @, n" A No Hazards.
f) S/ j6 D. w- a6 z
8 [0 V; N) d% q7 V% ^( o( _ Traces Layer 2 TO Via Pads Layer 2
% ]1 d! O) k* h! W% b No Hazards.- L. m( E1 C+ \7 W" n% X# ~
$ e Y! N8 Z# W. J/ e& R5 T% G Traces Layer 2 TO Via Holes Layer 2! i7 M% u6 u. J" Z" m7 o/ G6 W
No Hazards.' ^- j. b! d/ @3 S# a$ U' L4 g
) ^6 X$ X, I w
Part Pads SMD Layer 2 TO Part Pads SMD Layer 2# P8 j+ X7 \" Y
No Hazards.
8 V! e# f" b8 X0 T( u* o; o! J0 l) m- h0 ^7 g% T
Part Pads SMD Layer 2 TO Part Pads Thru Layer 2
3 h5 a8 y% |2 n% x No Hazards.8 y' h% p! w* F
. L1 B6 `7 z9 t" I. P _6 ^8 P
Part Pads SMD Layer 2 TO Part Holes Layer 2
/ q7 L( c5 |8 ^ No Hazards.
+ ^$ H, V9 T# _# R9 @" S* `
6 k& I+ e1 p' ^% Z5 H y Part Pads SMD Layer 2 TO Via Pads Layer 2( ^: i: J- C" o, ~& N$ X. L- r
No Hazards. x1 W1 r3 W: X a
/ o6 _' N, W" L
Part Pads SMD Layer 2 TO Via Holes Layer 2" g! b( ?1 W5 [0 g, _8 Y- A
No Hazards.1 l- ~$ `3 ?! ^4 M G O% v" |
. L) M7 d; z7 P6 U2 s* ?$ @6 ?, i Part Pads Thru Layer 2 TO Part Pads Thru Layer 2
% k! E7 J7 C3 I No Hazards.% e# p8 J7 d* C
1 W9 `2 e* x1 Z: b2 S5 }; W! @
Part Pads Thru Layer 2 TO Part Holes Layer 2
) x9 P* {* r! ^& T4 U8 ~; S: ] No Hazards.& y! Q0 e2 c2 r* y% d6 f* i
5 |6 U' F+ L3 F Part Pads Thru Layer 2 TO Via Pads Layer 2
# ]' W! Y3 U+ C3 F0 p No Hazards.
' n9 H0 m, u6 q' ?1 L5 J0 T6 m9 O, | U: h) L5 P7 N
Part Pads Thru Layer 2 TO Via Holes Layer 28 ^4 O) f' b" z5 L0 a
No Hazards.
3 E* S: [; ?4 r& c
& Q1 {5 P2 P5 @ j Part Holes Layer 2 TO Via Pads Layer 21 w/ ^) h5 M5 u5 g$ L0 e- y
No Hazards.' T' u, H4 I3 ^+ r2 L3 Y, g1 o
2 p0 X, x/ H3 H* v1 P% ~
Part Holes Layer 2 TO Via Holes Layer 2
" v& ^% w2 [, U0 V, o; o8 z No Hazards.
2 U8 ?/ U3 X1 ~# H. t4 c4 G1 y/ N* j' R
Via Pads Layer 2 TO Via Pads Layer 23 O4 |2 y3 m' e" S6 \) H+ |
No Hazards.
1 r0 h# ?+ A; w4 k1 P, m% L5 u! L
: N4 h2 _9 x0 q5 Y ] Via Pads Layer 2 TO Via Holes Layer 2
0 x* H2 A$ j9 j! A2 y5 J No Hazards.- x/ q6 O/ K1 \# C. D0 t0 X' I. Q
4 K" O# c( c h* f2 ~: n$ \
Via Holes Layer 2 TO Via Holes Layer 2
& k4 B8 z, B/ M1 Z% K$ C No Hazards., y. ?0 Y3 M, C4 O3 _% [
9 Q! ~* R# `8 w) T4 n5 ~/ c8 i! ~ ^: T( v: f, g, i- j3 z4 t
Total Hazards Found : 40 } o' _3 ~8 ?0 G" J' i( L- u" b5 c
, f' ?$ x, B6 }0 l; A
H0 a$ @) w v5 C' I* C1 r" n
0 Y* h( `8 |( A
, t! q! q2 U. U/ p0 Z1 A Planes Clearances And Rules
8 z Z" C6 R! r2 `6 @ ---------------------------
) J" }8 @' V/ v" l$ E( m5 c
: l3 P3 x/ J2 u5 j Positive Planes Layer 1 TO Part Pads SMD Layer 1
& U4 J7 e1 J) }8 U No Hazards.
4 [! S' ~+ l0 I, g# I" y; C
( B' } x2 q: I) n* a& e Positive Planes Layer 1 TO Part Pads Thru Layer 1
$ `9 h- z5 v* B$ D* y) ~: U No Hazards.
3 \" c' G& d: |# H/ G
7 {1 N& C }4 u; s) }3 r4 Q Positive Planes Layer 1 TO Part Holes Layer 1% Y$ e' g' l: X# O
No Hazards.
2 V1 F. }% ^8 W; @
3 E; v0 i5 i G; X @ Positive Planes Layer 1 TO Positive Planes Layer 1
_. l. P* A z" o) o No Hazards.
* l, ^* o. [( h2 m2 I; i7 u4 W6 w5 B t) c4 T. }( F
Positive Planes Layer 1 TO Route Border( [* c! i. l+ J6 b/ ]- F. [
No Hazards.: [3 r& j/ ^" ~* j3 S
1 v: }- g7 |/ {, \( H6 e Positive Planes Layer 1 TO Traces Layer 1
4 `. r# v# \0 l2 L a No Hazards.
$ h, F7 d" m/ d) s; k: N+ e) g& q8 I& g3 z+ F
Positive Planes Layer 1 TO Via Pads Layer 10 B: ~. O/ w! J$ s+ t
No Hazards.
/ ]! W) M( @( C1 e# F3 m
% F( d) P' \+ v' Z' ]. X$ |8 k Positive Planes Layer 1 TO Via Holes Layer 1
7 r1 m4 N6 D' X' {5 G* c No Hazards.
r6 P A+ i+ g1 ]; z* E3 R# V
/ L0 S; l5 u; A Positive Planes Layer 2 TO Part Pads SMD Layer 2: z4 U8 U6 A/ J" x5 I
No Hazards.
0 @* D. d7 X M% }
& p$ a8 d, d9 }* j Positive Planes Layer 2 TO Part Pads Thru Layer 2
$ [: N* E) `% c O' S. t' v No Hazards.
. M3 e# i1 v( J4 c: Z( I. f# m. T: @# M! F: d
Positive Planes Layer 2 TO Part Holes Layer 25 j4 s( u- z7 o3 K6 F% F
No Hazards.
+ Y' o" {- m4 D0 u3 S( J R8 p0 ?$ \/ N
Positive Planes Layer 2 TO Route Border2 J6 n) v+ j0 S( @( m' s
No Hazards.
8 j& j* Q4 [5 F8 _* n
) a7 ?1 o6 B$ E2 H2 ~7 p Positive Planes Layer 2 TO Traces Layer 2* J h! W: k. }# [+ J. ^; S
No Hazards.0 O. l, g: U8 t, K
5 `" m: y3 z3 V e7 B2 C
Positive Planes Layer 2 TO Via Pads Layer 2
& q" z: M/ d# |8 L Z1 @4 B6 d9 ?! I7 X; V No Hazards.2 w0 X/ m6 {7 [$ a; [0 M
+ ?5 |* R/ h7 @8 X Positive Planes Layer 2 TO Via Holes Layer 2) P. G( A9 j$ s# {, I
No Hazards.
& t% C2 |3 g4 L/ a! g( {( l* D6 b- g, w: V
3 x: t. x; i! @4 w
Total Hazards Found : 0: B0 ?3 X- k; Y' k
$ f. _* \2 H+ y; f: |( n" C
Z* ]/ `- \, F% L" {& ]0 O- p( d1 I: a* X* U) G
. Z5 }) A4 [) o. ]# p: p
Non-Net Class Element To Element Clearances And Rules& k( n4 }5 T- n) j
-----------------------------------------------------
% j- e' m9 `8 u
( `1 ~, S: i* i' ?" V6 U, J Route Border TO Via Pads Layer 1 Clearance: 0mm" u, H# A6 }' n
No Hazards.
! C& Y3 ~+ A, U" }- U* {6 a7 `- s% }- h! M P9 p( z
Route Border TO Traces Layer 1 Clearance: 0mm. F9 G9 _( [( s8 Y" {( ?
No Hazards.
: n" P# A! q. h. N1 w1 p7 o
# f& L) D1 N% `5 ` Part Pads SMD Layer 1 TO Route Border Clearance: 0mm
- r3 u( X0 N" k, F; Z4 n- J9 G0 f7 P% p No Hazards.0 J s8 E1 \; k1 a% x
: Q& R2 G) m+ L2 k% N5 l/ K Part Pads Thru Layer 1 TO Route Border Clearance: 0mm, B- ]- I; P! h3 [1 M- T
No Hazards.
9 P1 C/ t3 e/ ~ f: c0 j5 {: |( `- t P1 A. W
Board Outline TO Part Pads Thru Layer 1 Clearance: 0mm
' w; _7 G1 K: p! E6 j# C No Hazards.
' @! C9 ~# ^1 L$ D0 O8 E
" R( A7 G h+ q( p- U1 \ Board Outline TO Via Holes Layer 1 Clearance: 0mm
3 C; _3 j7 q+ Q8 T# S9 @# o, q No Hazards.6 |% e/ ~7 D2 P9 C7 `3 o! u+ x
- s" B8 l% r1 v5 d Board Outline TO Via Pads Layer 1 Clearance: 0mm l9 K8 K/ h8 I# ], }3 c8 i+ Z) |
No Hazards.
/ d0 e' k. i& R9 X) i, ~5 n. v# {1 j4 ]+ i4 y! T. p
Board Outline TO Part Holes Layer 1 Clearance: 0mm
$ H; a- e: v$ U: I3 k, h1 p" H7 ?, F No Hazards.
3 E2 w8 Y1 w# x: h J2 d$ a( j1 b+ o% A! y# a
>> Board Outline TO Placement Outlines Top Clearance: 0.15mm) u+ W3 K: y- X
Hazards Found : 2% l" a! L- f! O8 m4 R; }
6 D* G% c- ]) B9 u% }. b2 D! a& `
Board Outline TO Part Pads SMD Layer 1 Clearance: 0mm
1 h4 q( a7 i5 B8 L) m! P No Hazards.- }: w$ e9 o8 @# N) z) r" P
1 B& }5 Y$ h3 E+ \( ]5 |; p7 g
Board Outline TO Traces Layer 1 Clearance: 0mm
) l5 ?" v3 n' s& h* T No Hazards.5 k& [7 v2 x7 R5 ] D( {; F2 g; v6 X
6 ~& S4 O7 j& z5 L, \- g0 r. T7 K
Route Border TO Via Pads Layer 2 Clearance: 0mm. N% e! q) e- ]( P2 x
No Hazards.
6 J$ Z( c; ^/ }3 b ~/ R5 I8 [2 W9 {7 `1 v8 ^0 m; K6 f& d
Route Border TO Traces Layer 2 Clearance: 0mm
- K1 D4 a1 }. x7 e No Hazards.
$ T4 C* A& l5 y3 ~% B8 t' ^6 j% O* n
9 P& k. R( i& T) K- z4 }/ r8 ^0 s Part Pads SMD Layer 2 TO Route Border Clearance: 0mm1 h/ a" @0 C& s
No Hazards.: v/ c7 [) t! F9 V2 }) ?1 ^' C
. ~2 }. B' {" d: K Part Pads Thru Layer 2 TO Route Border Clearance: 0mm. c* ~- X6 i' M$ Z$ b1 a4 F4 A$ E
No Hazards.& X& H. G' e- D' J
. K) r, |- O) ?7 k# f
Board Outline TO Part Pads Thru Layer 2 Clearance: 0mm8 H' T' }8 r; F1 Q Q
No Hazards.% I5 ?0 a+ T6 v
/ b; `( L5 a* s; E
Board Outline TO Via Holes Layer 2 Clearance: 0mm
$ ^. f u4 j5 T+ [& O; R, B No Hazards.6 G2 R6 B" h l/ Q
0 k. N5 G/ s- W8 `+ C
Board Outline TO Via Pads Layer 2 Clearance: 0mm* C2 h% q: N, W8 P# S7 G9 d; s+ @
No Hazards.3 K' V' t/ {+ N+ u, C7 ~
% B% D8 S, V2 W- G. ] Board Outline TO Part Holes Layer 2 Clearance: 0mm5 k) v" h9 r( u' {/ C- d7 V" J5 p
No Hazards.
1 h( r. w1 }* V
0 @5 P# ^/ [1 A* d; g$ z& h Board Outline TO Placement Outlines Bottom Clearance: 0.15mm6 K( z- R+ H8 s0 _$ \
No Hazards.
4 U T9 ^/ N I6 m2 J, }4 D6 ?- U, U( @+ _6 I9 N7 x
Board Outline TO Part Pads SMD Layer 2 Clearance: 0mm$ `, v9 K. q* j1 Z; X) T3 n7 e
No Hazards. z# S+ U7 P- C! s" W
3 Z: G2 v/ ]: R1 U3 A Board Outline TO Traces Layer 2 Clearance: 0mm
: @9 `8 p( ]* p" P( V. t. ^ No Hazards., L5 }6 R8 ^* `" x* h
& b' l( o' n. C) o; }" w- v( h2 k0 T/ z( i. v$ Y( t
Total Hazards Found : 28 n8 S9 C0 H6 o! q( A
% W# }9 ^9 u+ |. J# {5 b* o2 a. w6 `6 Y- T
3 t! j* e+ O- A Total Proximity Hazards Found : 6
8 N7 R k5 u9 l* q y
?/ {) i8 e7 t% U/ T6 `. ~. {# C& F O! R4 a1 g. r7 g
" p x9 k; y8 `2 D; V5 z- M2 c/ g7 s( }
----------------------------
/ p/ {9 N5 R+ X0 E6 \ CONNECTIVITY & SPECIAL RULES% d% |) e! @5 m: e4 x2 w- ?6 {( S
----------------------------
/ c5 w# e. l- m# b4 a" }; P2 |5 U- g* }; H/ X) T$ A
! _9 A, F" Z) y4 H
Check For Unplaced Parts : YES/ @1 t. r6 y( ~2 @/ A
No Hazards.
" W3 r: x {8 b) m2 b {6 M6 C" J1 D1 F! g! _
) h. d2 m) @. Q$ u6 L3 \% u
Check For Missing Parts : YES5 ~% n' l2 z8 o" \
No Hazards.
) h$ c- ^ d6 T1 y& N% E9 w& x/ _; i2 W v
/ t2 F) ^6 n& a& S
Check Trace Hangers : YES; D7 d! D, M/ l7 o+ U% O
No Hazards.2 J8 ]# J) Q$ Q8 {! B' z
m' y6 s. N2 W' _8 d
9 c; t. b% D" s3 D7 `9 x" l Check Trace Loops : YES3 i/ c, e, l( _' c+ y# v- j
No Hazards.
. W& k B7 f4 P3 j& i3 ~; K
5 b5 V, N8 Z- o2 {
; a0 i! @- `; f6 R/ p Check Trace Widths : YES6 n7 L0 b1 G7 ]* _, C; t( R% K7 ?2 R7 U
Hazards Found : 122) r# j4 X% G, I- w2 {% e. i( O
$ w9 Y- O, D, e9 e. @2 x5 z- t0 x2 r9 r! E& m0 P6 \
Check Single Point Nets : YES. Z" E) ]1 \9 W5 U
Hazards Found : 1
3 ~9 N5 u' q7 o& C% W! T
: |; m. q; m: a0 ^
; R8 `8 c, e/ ]5 ? Check NonPlane Unrouted/Partially Routed Nets : YES
* w* D4 {1 H8 {+ E; K No Hazards.
) B2 c# p) q- a l- a% T* Y$ t. ]% n! L/ I2 q( k: C8 e
: M* v) t. {& ?1 U/ h6 C
Check Plane Unrouted/Partial Routed Nets : YES
- \0 d/ O: \4 e( N2 M+ K5 v No Hazards./ s8 @6 ^0 | K8 E+ _( w& O
2 t# x! c" m5 F# d
2 G: Q ^4 Z2 H- \, r3 R Check Routed Plane Pins : YES
* K2 W W& K9 a" M1 Q( Z+ J7 y No Hazards.# G9 `2 Y. p' ^
& ]( m3 R9 D0 L
5 z- q5 [0 m) W' a ]$ O. \( D* s2 S Check Plane Islands : YES$ C8 F7 S3 F5 J9 W* j: F7 ?' `5 h* h
No Hazards.# L8 E T9 J: Z2 z
* x6 C' u1 O. j( l9 A
4 _4 U& }! e1 z; O2 b; T Check Dangling Vias/Jumpers : YES
8 f1 T5 M1 {, Y- G5 H, o No Hazards.& Y% C; r( u, t* ~7 b. ?
( Z( W& L/ T6 B+ H" ~1 C/ }* E0 [7 L- [( U# U1 c& s8 J+ k
Check Unrouted Pins : YES; x8 _! P4 I0 P9 `
No Hazards.1 o _$ `5 \ j
- [% a! r/ v" U' W7 Z$ h3 l
8 S0 i9 \4 d# h, U
Check Routed Non-Plated Pins : YES+ S$ X7 e3 w# i% c: N7 d; D
No Hazards.5 D- [1 q4 G! ^0 W$ T. l. t3 d
3 o+ L( }: \/ L7 z; b$ _1 @$ e, ]9 S0 A, }8 L
Check Minimum Annular Ring : NO
, f. {) V1 A! R" f7 B
+ a3 c3 b. P5 T6 j$ `4 }: O
7 O) K8 O4 E7 _* A# I Check For Vias Under SMD Pads : YES5 p- B2 }9 ?+ K& s
No Hazards.
! \; R% b3 F+ b5 s* G* T! l7 z; [
) C9 T+ N8 C0 R( @3 T. M8 ^0 p1 ?7 v" ^& |$ G7 l$ `2 C9 R
Check For Vias Under Top Place Outlines : YES$ A+ c. b' ]$ b
Hazards Found : 52( T; O3 f! b! n7 F5 ]4 r$ }
, s" h# D8 f9 x, S0 w
# S& |, Y, {! f Check For Vias Under Bottom Place Outlines : YES
* a, G' l6 o7 |( c. Y Hazards Found : 10 b7 @/ G& V' G
! I+ I1 _+ S+ H5 U0 b5 d. @7 h9 g
, J2 H# J R4 r5 N) M
Check For Missing Conductive Pads : NO0 y: m, k+ Z( O: w* {3 Z0 u6 x
, o9 N" Z) n; T6 A0 i) [# m5 A8 c( C4 z5 z) h
Check For Missing Part Soldermask Pads : NO
/ |2 y9 ?* R; W7 |& D, W9 ?" l+ B- q0 ~# T$ _( w2 p; K* ^- S# b0 o
) h6 z0 O7 j8 [. x: C- } L% v* R
Check For Missing Via Soldermask Pads : NO
9 q' ?: E, y& Y
$ l3 x l& D( n2 P+ G
' Q8 d, J, [- j0 q% L% ^) u Check For Missing Solderpaste Pads : NO& n' W7 z( e! E; y
9 I$ R+ w Q# y& ~8 p5 o2 G
! l$ `$ Z `3 M
5 c' b5 q+ U# b5 \: m Total Connectivity/SpecialRules Hazards Found : 185
3 |. P7 g- p" _$ w- s. u) ^& H ?) |' {! b: o
& u4 ]: n# @! ]* B" @
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$ F1 o9 g" ~$ Q7 o# N Total DRC Hazards Found : 191" f4 [( ~5 O8 _: }/ h
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$ s; D" {+ }, p! [1 g7 X0 U, @$ S5 w 08:00 AM Tuesday, September 09, 2008
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* {' u$ t; O. Z' H# `6 C以上是我做的板子的DRC结果，% j @. | M4 O7 e) T/ C
Check For Vias Under Top Place Outlines : YES
5 W, `1 s' t7 K8 D6 B% T- n. k7 y Hazards Found : 52! I5 s0 H0 c0 n2 E5 a& w
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3 D2 u) h" z3 o Check For Vias Under Bottom Place Outlines : YES" o# i: w U% B0 o m- m2 N- J
Hazards Found : 10
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; Z* }8 W. n4 ], H) v. v其中元件的放置框内打孔有报错，怎么能让它不报错呢？ |
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发表于 2008-9-9 10:18
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淘帖
支持！
反对！
楼主