这段文字如何理解呢？为何会进入亚稳态？

mengzhuhao

这段文字如何理解呢？为何会进入亚稳态？

1 f- I5 j5 X6 \9 e2 Q; \If the asynchronous reset is released at or near the active clock edge of a flip-flop, the output of the flip-flop could go metastable and thus the reset state of the ASIC could be lost.

mengzhuhao

The biggest problem with asynchronous resets is that they are asynchronous, both at the
0 g3 U" r2 r0 H0 ]* R+ M( Y* Lassertion and at the de-assertion of the reset. The assertion is a non issue, the de-assertion is the
" X9 `0 ~5 {5 ^- n  v$ p* dissue. If the asynchronous reset is released at or near the active clock edge of a flip-flop, the
3 h# N1 x. B/ u  B4 E) V0 ^output of the flip-flop could go metastable and thus the reset state of the ASIC could be lost.
' T* @, z3 n) [' |6 uAnother problem that an asynchronous reset can have, depending on its source, is spurious resets
due to noise or glitches on the board or system reset. See section 8.0 for a possible solution to
reset glitches. If this is a real problem in a system, then one might think that using synchronous
  Z# _  ?( d4 ]) l' yresets is the solution. A different but similar problem exists for synchronous resets if these
1 Z  H# `9 P3 s( Hspurious reset pulses occur near a clock edge, the flip-flops can still go metastable (but this is
$ y7 n" D6 _& dtrue of any data input that violates setup requirements).