这段文字如何理解呢？为何会进入亚稳态？

mengzhuhao

这段文字如何理解呢？为何会进入亚稳态？
+ }0 \$ Q! [4 a7 z" [& \: |2 U
' ^$ S2 V. Y# \) k, _If the asynchronous reset is released at or near the active clock edge of a flip-flop, the output of the flip-flop could go metastable and thus the reset state of the ASIC could be lost.

mengzhuhao

The biggest problem with asynchronous resets is that they are asynchronous, both at the
4 U8 Q' N9 B0 p* I; E; @  ^assertion and at the de-assertion of the reset. The assertion is a non issue, the de-assertion is the
issue. If the asynchronous reset is released at or near the active clock edge of a flip-flop, the
output of the flip-flop could go metastable and thus the reset state of the ASIC could be lost.
' ?% H% R; k$ Z* x1 O3 EAnother problem that an asynchronous reset can have, depending on its source, is spurious resets
+ W# g: x: [* W& X& o$ Y  Ndue to noise or glitches on the board or system reset. See section 8.0 for a possible solution to
reset glitches. If this is a real problem in a system, then one might think that using synchronous
resets is the solution. A different but similar problem exists for synchronous resets if these
( _# R; A; F1 O% M/ X: Rspurious reset pulses occur near a clock edge, the flip-flops can still go metastable (but this is
true of any data input that violates setup requirements).