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http://dl.vmall.com/c0fu1auqa8
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% a g [0 x* ~3 b" k! }4 wDATE: 02-14-2014 HOTFIX VERSION: 023
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CCRID PRODUCT PRODUCTLEVEL2 TITLE8 |4 n m( _* c& q2 ~& c
===================================================================================================================================
5 `6 p; E0 r, I5 E. R1120183 F2B DESIGNVARI Variant Editor Filter returns incorrect results.
* m6 A0 f u. t0 M) E& N1202715 SPIF OTHER Objects loose module group attribute after Specctra8 {7 F& [' F1 A. t
1203443 ADW LRM LRM takes a long time to launch for the first time
* W' C1 v5 l1 m: h. O* U" `: S1207204 CONCEPT_HDL CORE schematic tool crashed during save all) H m; ~. Y& H9 `
1222101 CONCEPT_HDL CORE Pins are shorted on a block by the Block's title delimiter1 K6 }2 x, T/ Z" [6 X5 N' P
1223709 FSP FPGA_SUPPORT Need FSP model of Altera 5AGZME3E3H29C4 FPGA: b) C$ E" r* g* r6 ~
1224025 ALLEGRO_EDITOR INTERFACES The 3D viewer when working on a brd file shows package placed on BOTTOM side of my board while it is present on TOP side
- @. C$ U4 J8 c2 U, P* h! o6 p* ?1225591 F2B PACKAGERXL Aliased net signals starting with equals sign are not resolved correctly in cmgr
3 Y0 U8 r' D" ]7 M1226480 ALLEGRO_EDITOR EDIT_ETCH Routing time is took to double increase when using the Add Connect because DRC is Allowed.
' p+ t ]1 j2 \6 |' N: b2 ?1229234 FLOWS PROJMGR Can't open the part table file from Project Setup& }! ?5 h: z2 E
1229555 ALLEGRO_EDITOR ARTWORK IPC-2581 not recognizing pin offsets correctly.
. Z2 ~0 |2 L' u- I. H1229610 FSP FPGA_SUPPORT New FPGA device request - Altera Cyclone V ST: 5CSTFD6D5F31I7
( {: D E6 @' L1229664 ALLEGRO_EDITOR SHAPE Shape not voiding different net pins causing shorts with no DRC's6 ?5 F, K; s* f* r; }
1232601 ALLEGRO_EDITOR MANUFACT Cannot add test point to via on trace./ k. ]. t3 d) j D3 [
1232772 ALLEGRO_EDITOR DATABASE When applying a place replicate module Allegro crashes
- M2 h5 a! ? I0 ]- o2 R1233216 SIP_LAYOUT DIE_ABSTRACT_IF Allow more than 2 decimal places for the shrink facor in the add codesign form
; k; \9 H# x* J( R# X1233690 PDN_ANALYSIS PCB_STATICIRDROP PDN IRDrop: Mesh mode in Report is incorrect.
) S# g3 s) E v1 f1233977 ALLEGRO_EDITOR INTERFACES single shape copied and rotated fails to create when importing IDX
, k9 t) s" N; a" Z7 t' T+ R1234357 SIP_LAYOUT SCHEMATIC_FTB DSMAIN-335: Dia file(s) error has occurred.3 q" Y; x5 f" f/ ]) V6 [. U
1234450 ALLEGRO_EDITOR INTERFACES clines, pads, etch shapes to be at the same level with the board when viewed in STEP viewer.
6 b+ u$ n2 U* x: M8 u! ]1235587 PSPICE MODELEDITOR PSpice Model Import Wizard does not display symbol graphics for DE-HDL Symbol
6 E/ ~: v5 N0 k) g6 X2 ^/ |' \1236571 ALLEGRO_EDITOR GRAPHICS Allegro display lock up and panning issues, ~) }& ?: K9 Y+ A
1237415 ALLEGRO_EDITOR INTERFACES Multidrill pad is exported with single Drill in the STEP File
) q9 X5 k, }7 P' M. \1237807 ALLEGRO_EDITOR SCHEM_FTB The line feed code of netview.dat |
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发表于 2014-2-18 16:44
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