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http://pan.baidu.com/share/link?shareid=437717&uk=3826038294+ I( Y$ M6 p# y1 S0 j, P
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r. v% w) [! d. ]) ZDATE: 05-24-2013 HOTFIX VERSION: 010+ F- U2 n9 `& X: u7 y5 X
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1 b+ c2 C1 X6 K; K k! MCCRID PRODUCT PRODUCTLEVEL2 TITLE6 {! i$ U; Q2 N1 \/ M! Y
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2 B6 y( P. k( B4 G1084716 allegro_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer
6 K4 V6 L: G( i9 H/ m1 p1111430 FSP CAPTURE_SCHEMATI Auto-resize the schematic sheet so that hierarchical block fits within border
! @ y: S0 H% a: h1119007 concept_HDL CORE PDF Publish of schematic creates extremely large PDF files. H' v3 s! q- e) P1 a
1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor
9 o( D: o- R' \1 Z/ {5 G0 m# r1124610 Pspice SIMULATOR Attached design gives "INTERNAL ERROR -- OveRFlow" in SPB116.6& ~5 B3 t0 h( P0 V) F" _; r
1125330 FSP CAPTURE_SCHEMATI FSP generates orcad schematics with components (Resistors) outside page border6 V- x: ]5 b2 G
1131775 ADW LRM LRM error with local libs & TDA
1 X7 F+ o6 x7 Y) [" c# L1 z( {, o1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP4$ z0 `4 a j( Y0 G
1132080 ALLEGRO_EDITOR PLOTTING Size of the logo changes after File > Import > Logo
) X6 a; g2 w0 ~1134956 SPECCTRA HIGHSPEED Route Automatic fails with error when Impedance rules are turned ON in Allegro CM.
! C7 S9 Y$ F. n- e% w% m- q' ^1135548 SIP_LAYOUT SHAPE This design shows two areas with shape shorting errors that should not occur5 F0 R7 F: y4 ]& m" z4 }
1138312 ALLEGRO_EDITOR MANUFACT NCROUTE is not generated for filled rectangle slot ?4 c- l: N0 H" g' R. f3 {- ?& R
1139433 ALLEGRO_EDITOR GRAPHICS embedded netnames not displayed or getting very small upon panning after exiting 3D Viewer.% U2 C3 [, Y, k3 y
1139509 CONCEPT_HDL CORE The LRM update changes npn device to resistor6 l+ l# m$ j+ W
1140752 ALLEGRO_EDITOR PLACEMENT Moving a place replicate module crashes allegro, w; Z! k- k& w+ ^$ [
1141314 SIP_LAYOUT SYMB_EDIT_APPMOD Design will lock up after changing the border using Edit Boundary in Symbol edior mode.1 ^; U- Z+ S' F, M1 Z( t
1141751 ALLEGRO_EDITOR INTERFACES Allegro Crashes with Export IPC2581.
6 t, c$ A/ M; F; S1142478 CONSTRAINT_MGR INTERFACE_MAPPER adding constraint to netgroup causes CM & PCB SI to crash
8 S. `5 ^) O, M S1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF
' _ m3 i5 P9 q4 }- n4 g& D1143199 SIP_LAYOUT DIE_EDITOR Enable bump remastering
( Z% P1 z% P# p* Z) J9 _% Y1 N1143654 SIP_LAYOUT DIE_EDITOR Add X&Y offset when adding or moving a pin in die editor) G, T; G' s/ l
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发表于 2013-5-25 09:24
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支持！
反对！
发表于 2013-5-25 10:29
