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http://pan.baidu.com/share/link?shareid=437717&uk=3826038294! f! p4 T$ @, L
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4 U* V( s' S5 ^DATE: 05-24-2013 HOTFIX VERSION: 010" n% Y2 Q: N6 \; Y) Y/ W
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6 u3 Z' M' X5 I% ]1 y0 {CCRID PRODUCT PRODUCTLEVEL2 TITLE+ X) [% T8 B+ G3 C5 ?- d& H( g
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0 x* y0 w5 d$ [* u* k1084716 allegro_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer
$ H5 Z) y( p+ t. v. y' u+ U1111430 FSP CAPTURE_SCHEMATI Auto-resize the schematic sheet so that hierarchical block fits within border8 [) }: I! K6 t' K. ~! _
1119007 concept_HDL CORE PDF Publish of schematic creates extremely large PDF files* [; X4 y& f5 V. w. F+ v- }
1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor
( [& m3 |! h5 H4 j1124610 Pspice SIMULATOR Attached design gives "INTERNAL ERROR -- OveRFlow" in SPB116.6- U5 Z- v9 W# C( S9 m
1125330 FSP CAPTURE_SCHEMATI FSP generates orcad schematics with components (Resistors) outside page border/ I* A- L7 ]5 h" ~5 i. j9 Y% i
1131775 ADW LRM LRM error with local libs & TDA
2 [3 B: |: {! R* _( H! Y1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP44 G; }; v$ @) b, ^0 [
1132080 ALLEGRO_EDITOR PLOTTING Size of the logo changes after File > Import > Logo8 @- x0 k0 A. a; i' R, ~3 ]8 h" z
1134956 SPECCTRA HIGHSPEED Route Automatic fails with error when Impedance rules are turned ON in Allegro CM.' [! V& ~/ ~8 P* T( x$ ]5 B
1135548 SIP_LAYOUT SHAPE This design shows two areas with shape shorting errors that should not occur
0 r3 h7 _ Y) P; U1138312 ALLEGRO_EDITOR MANUFACT NCROUTE is not generated for filled rectangle slot ?8 B! c ~' a& d
1139433 ALLEGRO_EDITOR GRAPHICS embedded netnames not displayed or getting very small upon panning after exiting 3D Viewer.' v: o4 U- ~; b
1139509 CONCEPT_HDL CORE The LRM update changes npn device to resistor# ^4 J" F# H+ K; c
1140752 ALLEGRO_EDITOR PLACEMENT Moving a place replicate module crashes allegro
# O% g/ M0 a; U1141314 SIP_LAYOUT SYMB_EDIT_APPMOD Design will lock up after changing the border using Edit Boundary in Symbol edior mode. X% i3 m2 y9 t9 Z+ o
1141751 ALLEGRO_EDITOR INTERFACES Allegro Crashes with Export IPC2581.( X, j" P7 M5 G
1142478 CONSTRAINT_MGR INTERFACE_MAPPER adding constraint to netgroup causes CM & PCB SI to crash
9 U- v+ X+ x% B: P7 q. v1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF3 E& s& p& N1 {! I/ V3 O) o. e
1143199 SIP_LAYOUT DIE_EDITOR Enable bump remastering
8 @" J6 Z& ]+ j2 n4 y( \% O1143654 SIP_LAYOUT DIE_EDITOR Add X&Y offset when adding or moving a pin in die editor
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发表于 2013-5-25 09:24
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发表于 2013-5-25 10:29
