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http://pan.baidu.com/share/link?shareid=437717&uk=3826038294
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DATE: 05-24-2013 HOTFIX VERSION: 010
+ G& W6 ?4 r0 m( q* c# z# V$ b/ n===================================================================================================================================, Q7 V, @& @) K+ }8 L/ U
CCRID PRODUCT PRODUCTLEVEL2 TITLE1 w6 k6 @& [- ?
===================================================================================================================================
/ H- b* i3 z6 { {. Y1084716 allegro_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer+ X6 _- K" ^9 q' z
1111430 FSP CAPTURE_SCHEMATI Auto-resize the schematic sheet so that hierarchical block fits within border
( n! }9 N& U& z9 F4 Z8 j1119007 concept_HDL CORE PDF Publish of schematic creates extremely large PDF files9 J* B; u$ N- \/ r2 c2 K
1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor
9 k. {. D8 c' Z, \8 O8 k+ r8 \1124610 Pspice SIMULATOR Attached design gives "INTERNAL ERROR -- OveRFlow" in SPB116.6
; J7 K0 _# `; {1125330 FSP CAPTURE_SCHEMATI FSP generates orcad schematics with components (Resistors) outside page border: Z6 d- t7 [- B. I% l
1131775 ADW LRM LRM error with local libs & TDA) Q2 I& X. v X+ P9 g
1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP4
) C2 B/ Y8 }+ q& K" R1132080 ALLEGRO_EDITOR PLOTTING Size of the logo changes after File > Import > Logo
2 [" j# L" u: P1134956 SPECCTRA HIGHSPEED Route Automatic fails with error when Impedance rules are turned ON in Allegro CM.
5 I5 T/ g: U5 v p$ Y1135548 SIP_LAYOUT SHAPE This design shows two areas with shape shorting errors that should not occur7 d8 N7 Z0 K% j I! M
1138312 ALLEGRO_EDITOR MANUFACT NCROUTE is not generated for filled rectangle slot ?
' G- c" w6 q. U9 x l9 h1139433 ALLEGRO_EDITOR GRAPHICS embedded netnames not displayed or getting very small upon panning after exiting 3D Viewer.. r" G( e1 W c+ ~
1139509 CONCEPT_HDL CORE The LRM update changes npn device to resistor1 n& B7 @4 ^4 J* n1 z; z
1140752 ALLEGRO_EDITOR PLACEMENT Moving a place replicate module crashes allegro
; R1 I3 k1 N/ J; h& I. r& ^/ @1141314 SIP_LAYOUT SYMB_EDIT_APPMOD Design will lock up after changing the border using Edit Boundary in Symbol edior mode.& ^1 L' Z! R% H- q# S! l& @
1141751 ALLEGRO_EDITOR INTERFACES Allegro Crashes with Export IPC2581.& A0 Z2 J% v n0 o! P
1142478 CONSTRAINT_MGR INTERFACE_MAPPER adding constraint to netgroup causes CM & PCB SI to crash
7 U3 B% J5 [; u `7 M1 h1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF8 Q; G( X' }: G0 n5 B2 f8 q
1143199 SIP_LAYOUT DIE_EDITOR Enable bump remastering
3 G" y' T0 H8 C: q1143654 SIP_LAYOUT DIE_EDITOR Add X&Y offset when adding or moving a pin in die editor6 C0 y) u8 g( y# b
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发表于 2013-5-25 09:24
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反对！
发表于 2013-5-25 10:29
