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http://pan.baidu.com/share/link?shareid=437717&uk=3826038294
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+ L& p0 r, {- n0 ~# uDATE: 05-24-2013 HOTFIX VERSION: 010
2 R* i; K9 C# X, y1 K& X0 K===================================================================================================================================
$ J: i% g' W0 V& b* TCCRID PRODUCT PRODUCTLEVEL2 TITLE% ^, t4 k7 ]$ G7 S. Z
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1084716 allegro_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer* Z s V |7 d( L. S! w; |
1111430 FSP CAPTURE_SCHEMATI Auto-resize the schematic sheet so that hierarchical block fits within border
g5 v" W3 e2 X% j( r3 d1119007 concept_HDL CORE PDF Publish of schematic creates extremely large PDF files
5 D3 Z7 k: k# D9 G, x$ }1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor0 r, j0 e* z( t( u6 {
1124610 Pspice SIMULATOR Attached design gives "INTERNAL ERROR -- OveRFlow" in SPB116.67 z0 U. M5 f! ?+ N+ I& x
1125330 FSP CAPTURE_SCHEMATI FSP generates orcad schematics with components (Resistors) outside page border5 Y' c$ K2 P& \ O
1131775 ADW LRM LRM error with local libs & TDA
/ z+ q/ L4 J; ~" [2 q2 b1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP46 F3 O8 s, M; z$ m
1132080 ALLEGRO_EDITOR PLOTTING Size of the logo changes after File > Import > Logo! i5 v/ A1 J- |, H& Z' |1 Q6 h% V* y
1134956 SPECCTRA HIGHSPEED Route Automatic fails with error when Impedance rules are turned ON in Allegro CM.9 H" ~. L/ M8 r, H5 a* E
1135548 SIP_LAYOUT SHAPE This design shows two areas with shape shorting errors that should not occur* ]- }# x' ?1 e9 \* h( I X6 U
1138312 ALLEGRO_EDITOR MANUFACT NCROUTE is not generated for filled rectangle slot ?
7 i% A: ~9 s2 E$ D3 f2 ~2 ?1139433 ALLEGRO_EDITOR GRAPHICS embedded netnames not displayed or getting very small upon panning after exiting 3D Viewer.+ O; l- k; a4 p* o2 U
1139509 CONCEPT_HDL CORE The LRM update changes npn device to resistor
8 R, _$ I, c2 G1140752 ALLEGRO_EDITOR PLACEMENT Moving a place replicate module crashes allegro
V# ^. y: S* e6 X* E! {1141314 SIP_LAYOUT SYMB_EDIT_APPMOD Design will lock up after changing the border using Edit Boundary in Symbol edior mode.
1 F, W8 L1 A3 v2 u' R, L" J1141751 ALLEGRO_EDITOR INTERFACES Allegro Crashes with Export IPC2581.
( A4 w6 n# Z7 R# L. F1142478 CONSTRAINT_MGR INTERFACE_MAPPER adding constraint to netgroup causes CM & PCB SI to crash
6 G& z$ _ I4 S' H1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF8 Q. @3 K" @; ]: I) @0 l
1143199 SIP_LAYOUT DIE_EDITOR Enable bump remastering
6 [9 Q$ N! ?5 {# ~1143654 SIP_LAYOUT DIE_EDITOR Add X&Y offset when adding or moving a pin in die editor# _ `$ i: d9 K0 [2 l
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发表于 2013-5-25 09:24
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反对！
发表于 2013-5-25 10:29
