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本帖最后由 yueyuan2003 于 2012-12-17 21:14 编辑
0 [5 m8 ~% m/ c& L7 X3 X% O4 k% d* A5 F8 J* k4 v; _) Q
别的地方找到的更新说明，其实干嘛老是跟着公司更新软件啊，我就觉得16.3挺好的，功能就很好了
: z8 H; ]1 `0 U1 c, t i$ ^DATE: 12-18-2012 HOTFIX VERSION: 0018 f2 c0 {* C$ {# f, ]6 a
===================================================================================================================================" U) L5 d; o, M% i1 j0 ~. w+ K
CCRID PRODUCT PRODUCTLEVEL2 TITLE
8 B8 `9 R0 W: t& v1 p; T6 f===================================================================================================================================* c4 G0 z3 W+ M
501079 ALLEGRO_EDITOR MODULES Enhancement for Module swap function similar to component swap. I1 C. d- e3 g
745682 CONCEPT_HDL CORE Attributes window requires resizing each time DEHDL is launched
( y& n# u' o. F A" A* `825846 CONCEPT_HDL CORE The module_order.dat file gets corrupted' M) ]7 Z; p8 o* C. G5 ?
871886 CONCEPT_HDL CORE Browse button in Signal Integrity window of DE-HDL option causes program crash
b, x8 {+ L+ a# D4 |( L9 N; p891439 ALLEGRO_EDITOR INTERACTIV moving cline segments
2 w" `: ~4 a$ _% T3 M898029 CAPTURE PRINT/PLOT/OUTPU ENH: TCL:To show net alias clearly in print out if alias has underscore
& Y; C) X$ f& P; k! m0 u: _7 u923210 CONCEPT_HDL CORE Search with multiple properties does not show all properties
' a6 M- ^2 o! ?9 k$ p0 C938977 CONCEPT_HDL CORE Properties attached to standard/DRAWING symbol does not propagate to parts placed in the schematic+ m# H+ x/ x7 i* M1 x) m# ~+ ~
947451 ALLEGRO_EDITOR INTERACTIV Allow the tool to select multiple shapes when assigning a net to more than one shape.
6 y0 e7 q& a: @- N D5 I! B# _968646 ALLEGRO_EDITOR EDIT_ETCH The Cline to Pad spacing not followed for Multidrill pad it is more then minimum spacing& F8 d; h E; k/ Z" R1 {
976723 ADW MODEL_MANAGEMENT SI DML Model has to be provided the Auto Generate function for discrete components on DBeditor+ ^2 e, C: \8 q% ?# q. i( ]9 M
981767 SCM UI Add series termination in ASA will crash if both output and input pins are selected.2 {/ ~/ M' O) y: Q+ k7 T. v+ s& F, b
982273 SCM OTHER Package radio button is grayed out
& X1 @0 D/ X) @ H+ y988438 CONCEPT_HDL CORE Visible constraint disrupts MOVE command
" Y+ o8 n" T6 L: A) R4 X989471 ALLEGRO_EDITOR INTERACTIV Functionality to zoom to the selected object in Pre Select Mode+ j1 v( l& D% f( w+ Y0 |/ {+ W: ]% Y3 Z" L
993562 CONCEPT_HDL INFRA After upreving the design save hierarchy is leading to WARNING(SPCOCD-34).
! I9 n0 [+ W5 I2 b996577 SPECCTRA ROUTE Specctra not routing NET_SHORT connections& X( Y# l5 L' g7 `0 |1 S" \
997992 CONCEPT_HDL CORE Why are Page Numbers not enumerated correctly when multiple TOC Symbols are used?# o' \$ [1 _* j1 N8 ]+ [% s
1001300 PSPICE MODELEDITOR BUG: Simserver crash with encryptedm model
4 K; R W" S& m/ ~1 o `& ~1010124 PSPICE SIMULATOR Monte Carlo summary doesn't list all the runs in case of Convergence error in one of the runs
0 ~! B' n+ C$ p. `8 [1013656 SCM OTHER create diff-pair should honour diff-pair setup or ask user for positive negative leg
% r# v; |, E4 {* p1013721 ALLEGRO_EDITOR EDIT_ETCH Routing near a 2x3 multi drill padstack does not maintain the spacing constraints.$ \. B8 o- d' K+ _- t. k
1016859 SCM REPORTS dsreportgen exits with %errorlevel%
' P* D( r' s! D: {1018506 ALLEGRO_EDITOR INTERACTIV Edit copy with retain net of via will assign net to pin2 o0 d4 w" k( d6 O% @( [
1020746 CONCEPT_HDL OTHER PDF Publisher tool behavior inconsistent between OSs
F& z, U% I0 Z0 @1020798 SIP_LAYOUT SHAPE Shape not voiding on layer 2 causing shorts
6 i( i$ L# Y- u+ G/ E* e% f4 K1023051 SCM UI Wrong and incorrect message is generated while adding connectivity in SCM matrix view � DSTABLE-1401 Q: n$ ], ]# B% m
1023774 APD WIREBOND After "xml wire profile data" is imported it isn't reflected to actual wire.
/ d, {' i# ^% P. p ?1023807 SPECCTRA GUI Unable to close SPECCTRA using File > Quit or by clicking on standard window red close cross button
+ v7 E' \$ X4 f8 u* Q8 I, Q1 z: f6 ~1024239 ALLEGRO_EDITOR INTERFACES DXF pin location is moved when I execute DXF out) T/ F$ N3 e- A% r% c5 |! _/ q( X
1028237 CONCEPT_HDL HDLDIRECT Error binding design when generating simulation netlist* ^' } V v2 P& U) q
1030591 CAPTURE LIBRARY Library Correction utiltiy locks the library and deosn't frees it even after being closed
0 @2 q! e3 d7 {: K1035624 CONCEPT_HDL CORE Options pre-selected when launching base product
. L1 d D% ]0 F$ t9 f1035896 SIP_LAYOUT ASSY_RULE_CHECK Rule Wire Length under Wire on line in Assembly Rule Checker doesn't work correctly
4 }- x6 j' H) i$ g6 j2 w1036580 ALLEGRO_EDITOR MODULES Module created from completely routed board file has lot of missing connections in it.* c& y: O1 l# O# m+ [' Q$ ~
1037345 ALLEGRO_EDITOR INTERACTIV Enhance Allegro's Snap-To tools to select the origin of a sub-drawing(clip file)
& k( o6 V& F* I T/ d$ ^4 b1038180 ALLEGRO_EDITOR DRC_CONSTR BGA escapes not being calculated in phase tol# B: h5 `. k1 b
1038285 SCM UI Restore the option to launch DE-HDL after schgen.
; h# G( g( }% H7 c* ]. e1038371 ALLEGRO_EDITOR INTERFACES Import > IDF fails with error "(SPMHDB-187): SHAPE boundary may not cross itself."# }2 W8 l. e5 q- ]6 E$ l
1038577 ALLEGRO_EDITOR DATABASE Modifying Void crashes Allegro
- N( O6 b* L: g: x) X1039112 ALLEGRO_EDITOR ARTWORK Antietch and Boundary layers deleted when Match Display selected8 q1 o: k; i/ ^- w
1039147 ALLEGRO_EDITOR COLOR Need an option to change color of Text marker and Text select in Display listing) J K2 q B, m6 }
1040653 ALLEGRO_EDITOR DATABASE Cannot update netlist data, ERROR(SPMHDB-121): Attribute definition not found.+ N9 G6 \; B9 y7 I; \
1041368 APD DEGASSING The Degas_No_Void properties assigned to Cline does not work.1 K9 i5 i) w6 e' R7 j& s
1041864 ALLEGRO_EDITOR MANUFACT Allegro crashes when opening the Backdrill setup menu
) H) a' z8 h, A/ _3 X1042199 SIG_INTEGRITY SIMULATION Waveform list was not refreshed by switching tab.
" \6 T* j/ q) o! b9 p1 E$ ]! K {1042348 SIP_LAYOUT STREAM_IF GDSII export includes the full refernce path, breaks CATS flow
6 @% _: C5 t& L9 f! _2 P1043861 SIG_INTEGRITY REPORTS Derating values are NA in bus simulation report when derating table is not in working directory
9 d0 B `& X! ^4 g, a1 C1043903 GRE GLOBAL This design crashes during planning phases in GRE.* y2 S1 e& u. L' O+ J/ Q: T
1044029 PSPICE ENCRYPTION Encrypted lib not working for attached9 }2 @0 \& Y7 `. N$ M4 x4 h
1044222 ALLEGRO_EDITOR INTERACTIV Capture Canvas Image changes working directory
: W0 x& b# H; u9 o9 |/ U) m1044264 PSPICE SIMULATOR Why does the 'ORPSIM-15009:This device scales to 0.0 at this Temperature' Error occur.: \8 z" t7 ]/ S% l4 K( O' x! b
1044577 GRE CORE Plan > Topological either crashes or hangs GRE+ j) e4 L* _1 e5 ~5 h. W. W- E/ z+ z
1044687 TDA CORE tda does not get launched if java is not installed% H4 C+ y' \6 n: w: q2 _
1044754 SIG_INTEGRITY SIMULATION Incorrect waveforms when simulating with stacked die
& ], M% K9 j2 F& U: e6 x1045607 ALLEGRO_EDITOR OTHER Component get placed even after Cancel IDF in form. u- R8 K$ r( s$ ]
1045694 CONCEPT_HDL INFRA Why to package the design twice to pass the net_short property to the board?: R9 b- N8 r$ U3 B( z7 O" d
1045863 CONCEPT_HDL INFRA Customer had the crash several times when they run script with SPB16.51.& b* K, W8 z* ^4 C `; c/ y/ q
1046929 CONSTRAINT_MGR OTHER Unable to create physical of spacing cset after rename the default cset in design entry.
( |: T: g- a4 n4 `$ D. {+ H1047590 ALLEGRO_EDITOR SCHEM_FTB Buses created in Allegro-CM are deleted by netrev in traditional flow0 i0 I# T% p- ], L" F/ M O8 e
1047823 CONSTRAINT_MGR OTHER acPutValue predicate text not being displayed at bottom of Constraint Manager window.3 V2 V) E# ~3 r) {, M
1048403 ALLEGRO_EDITOR SKILL Allegro crashes opening more than 16 files with skill
/ K; K1 _) o0 ^' E; _. S1049262 ALLEGRO_EDITOR OTHER APD and extracta crash owing to Wirebond.
9 [# ]2 o3 I/ G. Z% I+ ^7 B1049303 CONCEPT_HDL CORE Block rename deletes schematic data immediately in 16.5
* \( y$ y& b. Q5 C0 r/ N+ K1049317 CONCEPT_HDL OTHER bomhdl with scm mode not working on RHEL in 16.5
8 F5 ^$ c0 w1 @3 X$ z" L+ L1049399 SIG_INTEGRITY OTHER Toggling z-axis delay in CM shows the same value
4 W+ _; ^+ _, P' o1049956 ALLEGRO_EDITOR DATABASE BUG:dbdoctor deletes fillets as design is migrated from old version
- s& O% p& g8 U2 L9 q8 `/ D1050408 APD DXF_IF Symbol has 45 degrees rotation in mcm but DXF doesn縯.9 @8 d6 t) A. ^( Q- ^
1050483 ALLEGRO_EDITOR DRC_CONSTR DRC has been waived but after updated DRC system generated a new DRC.
, u* F* Y' k: ?: g1 L: ?: d1050918 ALLEGRO_EDITOR MANUFACT Testprep Automatic generate testpoints with wrong padstack Itype in SPB165S026." H1 z- ~8 ~5 A+ O9 v) Y! s4 A2 G) \
1051588 ALLEGRO_EDITOR PAD_EDITOR Pad_Designer library drill report omits some drill holes
. u c' v2 ]+ m7 d; C) |1052005 SIG_INTEGRITY OTHER Huge difference in Z-Axis delay with the latest hotfix for 16.5 that did not exist in older ISR's of 16.5.7 v! Y& y9 g' G' e. f, y
1052045 ALLEGRO_EDITOR OTHER Bug - Thermal relief connects not sustaining 15 degrees component spin in version 16.5 unlike v16.3/ A( _% @2 o# \
1052449 CONCEPT_HDL COPY_PROJECT Copy Project does not update all relative paths in the cpm file
+ k$ J$ Z$ F9 G# p1052600 ALLEGRO_EDITOR SHAPE Adding a specific cline causing shape errors% n* H: U' A7 c0 |8 o
1052753 ALLEGRO_EDITOR DRC_CONSTR Allegro showing soldermask drc only when the symbol is rotated.
9 I- K6 K. O0 H' R* X1054235 ALLEGRO_EDITOR PLACEMENT Cannot place alt_symbols for mechanical parts.
' l5 X+ H1 E9 R. O& M9 Y/ m0 u1054269 ALLEGRO_EDITOR MANUFACT Backdrill Setup and Analysis crashes on attached design- X! { j' }4 }: E
1054351 ALLEGRO_EDITOR SHAPE Shape voiding fails for board having diffpairs with arcs7 F1 [9 { R* B$ D' z" U
1054456 ALLEGRO_EDITOR MENTOR mbs2lib incorrectly translates refdes label& r- L/ F% ^+ L
1055273 ALLEGRO_EDITOR INTERFACES DXF exported from Allegro has an offset in pad location for Y- direction.
. A, b( J1 U2 ], J ]- N1055328 CONCEPT_HDL COPY_PROJECT Project Manager - Project Copy, r+ h- O- p' m7 ~' X1 R3 k
1055481 APD SHAPE keepout does not clear shape unless it's picked up and dropped down( y [4 I% M6 a, o
1055729 CIS GEN_BOM Standard CIS BOM per page is not working correctly with option Process Selection( x" v4 h! E8 V3 A9 T
1056418 ALLEGRO_EDITOR OTHER PDF exports the blank text markers whether or not the markers are visible.
9 u1 v! Y7 b# j7 B% q1056579 CAPTURE OTHER Ability to define custom variables for titleblocks that update for specific variant views( C( U T% }6 W$ A2 T7 |+ Q8 U# A
1057003 ALLEGRO_EDITOR SHAPE Z-copy to create RKI does not follow board outline
# P- o! u, n( G9 k Z, _% f5 n1057976 ALLEGRO_EDITOR DRC_CONSTR No Same net Spacing DRC on attached design.
, D2 ?& v# W* f1058002 SIG_INTEGRITY SIMULATION Incorrect Xtalk sim netlist was created.9 B* q1 S$ s# Z" F; F
1058364 ALLEGRO_EDITOR SKILL axlTransformObject() is moving refdes text when only symbol pin is selected for move: k. ?( S9 F$ F, G
1058940 ALLEGRO_EDITOR INTERFACES IDF(PTC) out command output wrong angle value
; w, v7 i U/ a! e8 Q1059037 CIS PLACE_DATABASE_P What enables the Refresh symbol libs option under hte update menu in CIS explorer/ M7 Y0 k* m. M, I: u4 Y' Z8 s. s
1059389 ALLEGRO_EDITOR MANUFACT about back drill analisys report+ ]- R; s* }: X- u; [
1059901 CONCEPT_HDL CORE Global Property Change and <<OCC_DELETED>> property value.
2 V+ Z+ u6 A% G; B* ^3 Q, E- G- B1060428 ADW DESIGN_INIT ADW Flow Manager Copy Project fails to complete
2 o6 t2 N7 I. k; t+ v1 u1060589 F2B PACKAGERXL Packager Fails with ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance properties.
4 d0 G6 o2 c0 H9 R1060977 F2B DESIGNSYNC back annotate in 16.5 does not bring in already placed nets as global nets8 h% P. O5 x) k, J) @
1061223 CONCEPT_HDL CHECKPLUS What determines a passthru pin?
+ P; v: P3 `5 r, c1061424 CONCEPT_HDL CORE Customer creates <<OCC_DELETED>> property values.
! Z. t( n: {# e1 Y2 C; i$ b: [3 g& v1061572 ALLEGRO_EDITOR INTERACTIV Shortcut keys wont work after "Edit Text" command is finished.
$ Y7 {4 \7 s' R& t' }7 O1061659 ALLEGRO_EDITOR DATABASE Unable to return drawing origin to 00
- l, l0 h; g6 Z' \" H* R' ?1062558 APD DXF_IF If set both in X and Y offset DXF only get one and not get absolutely value in 45 degree rotation
9 }. S- |! M- m1062982 ALLEGRO_EDITOR MODULES Module containg partitions has been imported to the main design and cant be refreshed.
6 \+ N$ h U; |, y8 r1063284 PCB_LIBRARIAN OTHER PDV Save As is broken
$ O: H4 Z+ _3 o% ]) k2 v1063658 ALLEGRO_EDITOR SCHEM_FTB Allegro Import Logic does not remove library defined diffpairs
! @' k2 M9 k% ^# Q& S7 g1063778 CONCEPT_HDL CHECKPLUS The hasSynonyms CheckPlus predicate is not returning true for all global signals.
/ C" v+ [3 M* g9 h7 \1063924 CONCEPT_HDL CONSTRAINT_MGR Highlight the net between DE-HDL 16.5 and Constraint Manager.$ L9 T" D6 N: S* @/ H- q9 r. X
1064707 CONCEPT_HDL CHECKPLUS Rules Checker core dumps on design) \7 m j( n& @# p( f4 ]
1065124 PCB_LIBRARIAN SETUP PTF properties cannot be deleted from the setup in PDV
7 `& t* b: [0 L! k! m4 l2 n1065618 CONSTRAINT_MGR ANALYSIS DRCs on board but Constraint Manager shows the columns as green.5 u5 r9 ~) \6 ]% S+ d- B6 u/ @, h
1065641 PCB_LIBRARIAN CORE PDV symbol editor is crashing when deleting a group using delete or CTRL+X
# d7 B$ u5 L; ?* q# q/ K) C1065745 SIP_LAYOUT DATABASE The logic assign net command crashes the application
5 r3 a& b ?: Y: @) G i0 @1065860 ALLEGRO_EDITOR REPORTS Design crashes when running a padstack usage report4 ^( V" E# Y7 W5 v h+ b* ~% x
1066051 ALLEGRO_EDITOR TESTPREP Auto Testprep generation creates TP with Testpoint to Component Locatin DRC, e U* y; k4 L7 L# i2 b
1066318 CONCEPT_HDL CREFER Issue with LOCATION visibility in flattened schematic
+ w6 @- {( d W H1067339 CONSTRAINT_MGR ANALYSIS Relative Propagation Delay analysis in the Partition file seems very inconsitent.
& A ]3 q. M, L8 {; M% o0 z1067984 SIP_LAYOUT OTHER layer compare batch fails with write protected file
% z$ S- K. g) _0 J ^& A$ B1068425 F2B DESIGNVARI Out of memory message in Variant Editor while 縞hange properties� command
$ A' G0 p3 a8 f7 y5 a. R4 s1068547 ALLEGRO_EDITOR EDIT_ETCH Outward Fanout is not fanning out this 4 sided part as intended/ Q( C, ~2 O. L6 T! h) f. }8 @
1068966 SIP_LAYOUT DRC_CONSTRAINTS DRC update aborts on this design with ERROR -3000067! n- J. P& s- @
1069215 CAPTURE DATABASE Capture Crash on usnig a TCL utltiy to correct design: q" U5 h8 e4 g
1069517 SIP_LAYOUT DIE_EDITOR change die abstract pins tab default action from delete to modify
" J; v# L0 V( _1069915 ALLEGRO_EDITOR EDIT_ETCH Allegro hangs with when doing spread between voids
1 ^3 D0 s- [& ?1070007 ALLEGRO_EDITOR PLOTTING Export IPF omits drill figure characters for backdrill holes, i- J$ D/ v& i! Q
1071722 SIP_RF DIEEXPORT Virtuoso SiP Architect not writing out pins to the .dra needed for LVS flow- o* D) ?: \) P, E4 _
1072067 APD EXTRACT When expoting using Extracta oblong pads with anyangle are abnormal
( Y3 }6 X" R8 l9 P% d; y1072791 ALLEGRO_EDITOR DATABASE Database check cannot fix error and keep report the same issues cause artwork cannot export.* ]& @8 J* k: t
1072806 CIS EXPLORE_DATABASE Query tab in CIS explorer doesn't show searh fields in 16.6
. ]6 @( j; ]- ~! g- X4 [1072843 ALLEGRO_EDITOR PLACEMENT The move command that was present in the right mouse pop up menu during manual placement is missing in 16.5
3 L# z4 f$ U8 T6 N7 P8 @- O5 n1072904 SIP_FLOW SIP_LAYOUT Probe pins not being mirrored in Die Editor correctly in Chip Down mode.* g Y5 r7 t. G7 L n
1073237 SIG_INTEGRITY GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.
4 z# v0 o) W$ O7 d2 }1073445 ALLEGRO_EDITOR GRAPHICS 'infinite cursor graphics fail -ghost copies as you move cursor
7 p$ `7 N4 y; [5 \- e$ }1073464 SCM SCHGEN Schgen never completes.* L W2 w# N% S7 O: F% v7 v
1073587 SIP_LAYOUT OTHER axlSpreadsheetSetWorksheet command clears the cells in memory
/ ]+ o0 m3 x5 M: ?2 D3 m1073745 CONCEPT_HDL CORE Import design fails
, b; z5 ^9 f! D. W' |) m1 R3 x; w1073852 ALLEGRO_EDITOR INTERACTIV While doing a Copy Via use the last 'Copy Origin'. h' c |) h6 e
1074279 ADW DSN_MIGRATION Design Migration fails purge if there are cells with BODY_TYPE5 ?1 `0 u; g, |/ g0 [7 ^' t$ I0 t
1074791 CONCEPT_HDL HDLDIRECT User gets port exists in schematic but not on symbol message even though the port does not exist
# m1 @) v. c) ?! n n1075135 ALLEGRO_EDITOR DRAFTING Ability to edit dimension text block in Instance Parameter2 |! D1 n$ D$ J- e5 E# ?7 ~
1075151 ALLEGRO_EDITOR SHAPE Cannot change global shape parameter back to thermal width oversize after having used fixed thermal0 m2 o. |* v9 I2 T
1075256 ALLEGRO_EDITOR OTHER Import > IPF in 16.5 is dropping data.
# m% [2 {* o3 a9 V# E1075853 ALLEGRO_EDITOR REPORTS please add "PART_NAME" at Extract UI# Y* X1 K) {6 K4 e d
1075934 ALLEGRO_EDITOR DRAFTING Able to Changing Dimension Text Block* X6 ]1 j& z& z
1075955 CAPTURE SCHEMATIC_EDITOR ZOOM in 16.6 using key "I" on keyboard in not centered on mouse pointer8 ^2 l. N$ P) w6 X* ]
1075964 ALLEGRO_EDITOR SHAPE Shape voiding is not consistent in conjunction with odd angle and arc traces
, j: A; @6 q( p2 w" S8 @1076086 SIP_LAYOUT IMPORT_DATA missing wirebond after import SPD2
: ?* E9 ^* M4 `% c3 \4 M1076202 ALLEGRO_EDITOR EDIT_ETCH Allegro add connect causing crash after Hotfix4 \7 u: i! c; S! I* P+ M
1076205 CAPTURE PRINT/PLOT/OUTPU : Printing of User Assigned RefDes1 W" \3 C o) @+ d7 b6 ^
1076536 ALLEGRO_EDITOR DRC_CONSTR Embedded component which protrude out toward Top do not create DRC with Place Keepout on Top
1 k9 u2 V3 }5 [1076538 CONCEPT_HDL CORE Property visibility changes in attribute form not updated in schematic canvas.
0 A6 P) C; `7 D: H- c" }5 A1076655 APD DXF_IF Dxf does not get offset value if die symbol padstack has offset value
2 b( A, L' S: m: j* v$ a2 Y! v1076846 ALLEGRO_EDITOR EDIT_ETCH Grid snapping broken after slide in 16.6
( O* ^% ], {6 t, w. w/ _& x/ u1076891 ALLEGRO_EDITOR INTERACTIV Symbol rotation not displayed correctly when defined as a funckey
# O& m" Q8 T. ?1076909 ALLEGRO_EDITOR DRC_CONSTR Allegro crashes while placing modules from database
$ [, r: t; F' J1 {: @1077084 CAPTURE NETGROUPS Crash on selecting bus when Enable Global ITC is unset
+ o, h! r, ~& f1077169 APD SHAPE Shape > Check is producing bogus results.
% |2 V( O& M. M. x6 t! X1077572 ALLEGRO_EDITOR DATABASE Mechanical symbol created with 16.6 cannot be placed on board.
; C" M$ }2 I$ k4 i1077879 ALLEGRO_EDITOR SKILL Allegro Skill axlDBCreateFilmRec fails when 15th argument missing "draw hole only" for the first tim) v) l6 m0 J! M% |% k2 ~2 S
1078380 SCM OTHER Custom template works in Windows but not Linux
5 ^5 D' x1 T; E; ^ o2 u/ i' }8 q. S* ?, ?1078497 ALLEGRO_EDITOR INTERFACES Import DXF does not seem to work correctly.% U+ w6 R* ~, ^8 C/ H
1078682 ALLEGRO_EDITOR DRC_CONSTR Unaccetable slowness with Slide
: k* J0 l) H. A1079082 ALLEGRO_EDITOR PLACEMENT Swap components, gives error SPMHGE-616, when symbols instead of components are selected for swapping8 D0 G" e O5 |6 V
1079533 ALLEGRO_EDITOR PLACEMENT Swapping components in 16.6 results in Error "E-(SPMHGE-616): Symbol and layer embedding requirements do not match"4 C/ J0 Y' u! x$ j
1079937 CAPTURE SCHEMATIC_EDITOR ZOOM in 16.6 is non uniform on text |2 P6 v5 E' w; Z6 U1 k) C
1082582 ALLEGRO_EDITOR GRAPHICS Allegro hangs on a given testcase using the MMB zoom control
8 C, ~7 I2 `& P; R1082981 ALLEGRO_EDITOR SKILL Allegro crash while change the new symbol type as mechanical., {- F& g0 L6 W5 d& m2 n5 s
1083230 SIP_LAYOUT SHAPE Shape fill in 16.6 releaase not fillilng shapes as good as it did in the 16.5 release.$ _3 L$ Q7 K, [* ^/ P0 W( t( w
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发表于 2012-12-17 12:49
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