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本帖最后由 yueyuan2003 于 2012-12-17 21:14 编辑 3 p2 i5 x) M: W1 H7 n
8 E: U# u" J0 p3 p" b, Q别的地方找到的更新说明，其实干嘛老是跟着公司更新软件啊，我就觉得16.3挺好的，功能就很好了6 t9 t/ ~, j* a6 {8 F' Y2 U: y$ P
DATE: 12-18-2012 HOTFIX VERSION: 001
" f9 N3 [9 K8 b0 y* R/ G===================================================================================================================================: d3 i4 V0 |0 W. y. @
CCRID PRODUCT PRODUCTLEVEL2 TITLE2 U! u& O/ q' Y* U N! w
=================================================================================================================================== v2 x- [ E) j C+ P$ h6 b d. [3 H
501079 ALLEGRO_EDITOR MODULES Enhancement for Module swap function similar to component swap
- [) T# }6 a3 X5 t( n; J8 b745682 CONCEPT_HDL CORE Attributes window requires resizing each time DEHDL is launched! K8 t6 z7 w' }# X% `& M
825846 CONCEPT_HDL CORE The module_order.dat file gets corrupted
' c I# U, J# B3 r$ S5 J) s3 d4 Q871886 CONCEPT_HDL CORE Browse button in Signal Integrity window of DE-HDL option causes program crash
" ^, w; b; ~* d3 C* Z891439 ALLEGRO_EDITOR INTERACTIV moving cline segments
; Z! q; U! k, b3 Y5 y& B898029 CAPTURE PRINT/PLOT/OUTPU ENH: TCL:To show net alias clearly in print out if alias has underscore! \+ N8 B J7 f$ H
923210 CONCEPT_HDL CORE Search with multiple properties does not show all properties
/ w: A7 U, y: S" Z; ^* P1 V5 r938977 CONCEPT_HDL CORE Properties attached to standard/DRAWING symbol does not propagate to parts placed in the schematic
9 y, W5 P3 i( V; z2 d" F6 g% u947451 ALLEGRO_EDITOR INTERACTIV Allow the tool to select multiple shapes when assigning a net to more than one shape.
/ |7 M9 F0 X Z968646 ALLEGRO_EDITOR EDIT_ETCH The Cline to Pad spacing not followed for Multidrill pad it is more then minimum spacing
3 R W$ m9 G7 M' V+ x! B976723 ADW MODEL_MANAGEMENT SI DML Model has to be provided the Auto Generate function for discrete components on DBeditor$ |8 s( v/ m3 D) `- U, }9 S
981767 SCM UI Add series termination in ASA will crash if both output and input pins are selected.
: Q% ?- n% V q( ?' M982273 SCM OTHER Package radio button is grayed out
* c1 o! ~5 j! c* G. A988438 CONCEPT_HDL CORE Visible constraint disrupts MOVE command0 h3 U" J% A1 S1 u$ G& q. p
989471 ALLEGRO_EDITOR INTERACTIV Functionality to zoom to the selected object in Pre Select Mode
0 h( ^- t+ I- I9 g; ?993562 CONCEPT_HDL INFRA After upreving the design save hierarchy is leading to WARNING(SPCOCD-34).
4 h6 O; p) E0 |. [996577 SPECCTRA ROUTE Specctra not routing NET_SHORT connections" U% W5 k1 F9 l/ B1 j! I) F. I) }
997992 CONCEPT_HDL CORE Why are Page Numbers not enumerated correctly when multiple TOC Symbols are used?( b8 |0 Q9 | G4 K* `( X4 X
1001300 PSPICE MODELEDITOR BUG: Simserver crash with encryptedm model
, e( m7 ~, M5 @/ F1010124 PSPICE SIMULATOR Monte Carlo summary doesn't list all the runs in case of Convergence error in one of the runs
6 R: o) c$ Q# w# u$ A1013656 SCM OTHER create diff-pair should honour diff-pair setup or ask user for positive negative leg
$ S9 }( p1 h+ G M1013721 ALLEGRO_EDITOR EDIT_ETCH Routing near a 2x3 multi drill padstack does not maintain the spacing constraints.
5 E2 Z _6 W7 j0 l) C$ W( y. ?1016859 SCM REPORTS dsreportgen exits with %errorlevel%
' x4 {9 y* ~3 i- v1018506 ALLEGRO_EDITOR INTERACTIV Edit copy with retain net of via will assign net to pin
* a1 w0 L# V+ Z/ D) c) o& z1020746 CONCEPT_HDL OTHER PDF Publisher tool behavior inconsistent between OSs6 _; s% j6 N# }* x3 H" y$ b- O
1020798 SIP_LAYOUT SHAPE Shape not voiding on layer 2 causing shorts6 Q) s1 I9 _, k$ B( s
1023051 SCM UI Wrong and incorrect message is generated while adding connectivity in SCM matrix view � DSTABLE-140
/ S8 k, e1 \8 U6 r0 `8 s9 m1023774 APD WIREBOND After "xml wire profile data" is imported it isn't reflected to actual wire.+ K0 w) x7 R$ y# ^8 D: n
1023807 SPECCTRA GUI Unable to close SPECCTRA using File > Quit or by clicking on standard window red close cross button
, H4 b% Z. C. c6 B7 i1024239 ALLEGRO_EDITOR INTERFACES DXF pin location is moved when I execute DXF out/ v" r3 p% D8 E. Z( A ^' F
1028237 CONCEPT_HDL HDLDIRECT Error binding design when generating simulation netlist: A& {/ E! ~9 `( `- Q
1030591 CAPTURE LIBRARY Library Correction utiltiy locks the library and deosn't frees it even after being closed
5 H& T6 }( O' s3 R4 R3 M# h1035624 CONCEPT_HDL CORE Options pre-selected when launching base product& K H9 @6 `' j: l
1035896 SIP_LAYOUT ASSY_RULE_CHECK Rule Wire Length under Wire on line in Assembly Rule Checker doesn't work correctly
' |. M' w M' w ^' Y1036580 ALLEGRO_EDITOR MODULES Module created from completely routed board file has lot of missing connections in it.) m, v4 J( z$ }, @
1037345 ALLEGRO_EDITOR INTERACTIV Enhance Allegro's Snap-To tools to select the origin of a sub-drawing(clip file)2 j& G. l0 c' Z1 y) q- ]8 {8 X" |
1038180 ALLEGRO_EDITOR DRC_CONSTR BGA escapes not being calculated in phase tol
, [1 D# s: q& U0 x" {1038285 SCM UI Restore the option to launch DE-HDL after schgen.
2 P" @4 H) ?4 u, `9 m1038371 ALLEGRO_EDITOR INTERFACES Import > IDF fails with error "(SPMHDB-187): SHAPE boundary may not cross itself."2 F8 u! I3 ~) k
1038577 ALLEGRO_EDITOR DATABASE Modifying Void crashes Allegro
" R ^, x; l# z% N: p1039112 ALLEGRO_EDITOR ARTWORK Antietch and Boundary layers deleted when Match Display selected7 @3 Q1 ]7 W8 C7 O$ v) p9 u* u
1039147 ALLEGRO_EDITOR COLOR Need an option to change color of Text marker and Text select in Display listing
6 s4 y$ R( Y! R1040653 ALLEGRO_EDITOR DATABASE Cannot update netlist data, ERROR(SPMHDB-121): Attribute definition not found.
$ i/ x0 m( X$ V3 b; C; b! N1041368 APD DEGASSING The Degas_No_Void properties assigned to Cline does not work.' N/ V2 G6 E8 a8 O' z
1041864 ALLEGRO_EDITOR MANUFACT Allegro crashes when opening the Backdrill setup menu2 L1 P+ x. `& V2 ~
1042199 SIG_INTEGRITY SIMULATION Waveform list was not refreshed by switching tab.4 f6 n* w" W3 h/ w- l
1042348 SIP_LAYOUT STREAM_IF GDSII export includes the full refernce path, breaks CATS flow/ s3 Q1 m" J, F
1043861 SIG_INTEGRITY REPORTS Derating values are NA in bus simulation report when derating table is not in working directory9 m7 L6 p( f3 c; Y" W
1043903 GRE GLOBAL This design crashes during planning phases in GRE.
9 r% Q- l N; r: K* k+ q) d1044029 PSPICE ENCRYPTION Encrypted lib not working for attached
- f. Y9 R" t4 ~0 ~6 ~1044222 ALLEGRO_EDITOR INTERACTIV Capture Canvas Image changes working directory
8 X" c* a2 ~3 o8 n1044264 PSPICE SIMULATOR Why does the 'ORPSIM-15009:This device scales to 0.0 at this Temperature' Error occur.: a1 b& R0 d+ v) r: @' a+ @+ a
1044577 GRE CORE Plan > Topological either crashes or hangs GRE
0 M# z: @! W8 J# z# L4 E( a i1044687 TDA CORE tda does not get launched if java is not installed# O F: s$ R5 T
1044754 SIG_INTEGRITY SIMULATION Incorrect waveforms when simulating with stacked die
! u! a+ z0 \* d1045607 ALLEGRO_EDITOR OTHER Component get placed even after Cancel IDF in form.# E G7 T2 G0 u
1045694 CONCEPT_HDL INFRA Why to package the design twice to pass the net_short property to the board?
; d0 H* m! v- z7 u, ~1045863 CONCEPT_HDL INFRA Customer had the crash several times when they run script with SPB16.51.
2 M/ S/ s F9 f- I7 X1046929 CONSTRAINT_MGR OTHER Unable to create physical of spacing cset after rename the default cset in design entry.
; J* j L8 i4 K6 l4 O/ n1047590 ALLEGRO_EDITOR SCHEM_FTB Buses created in Allegro-CM are deleted by netrev in traditional flow. p1 Y) c J. V4 F, R9 }1 O
1047823 CONSTRAINT_MGR OTHER acPutValue predicate text not being displayed at bottom of Constraint Manager window.
3 v: L8 u2 b5 U' t0 y, e% d1048403 ALLEGRO_EDITOR SKILL Allegro crashes opening more than 16 files with skill3 W7 r9 o% M+ e& U( `& d
1049262 ALLEGRO_EDITOR OTHER APD and extracta crash owing to Wirebond.
9 n7 }2 t. k. M1049303 CONCEPT_HDL CORE Block rename deletes schematic data immediately in 16.5
/ t8 W0 U/ u* w+ f5 j" H1049317 CONCEPT_HDL OTHER bomhdl with scm mode not working on RHEL in 16.59 i: [- h7 f, l# }5 y+ }
1049399 SIG_INTEGRITY OTHER Toggling z-axis delay in CM shows the same value6 G* P, Q$ E* Z
1049956 ALLEGRO_EDITOR DATABASE BUG:dbdoctor deletes fillets as design is migrated from old version
$ Y5 G6 R# d. N) J8 q: `# B! l( v+ e1050408 APD DXF_IF Symbol has 45 degrees rotation in mcm but DXF doesn縯.
9 T2 Q1 n, E, p" `: j5 @* N1050483 ALLEGRO_EDITOR DRC_CONSTR DRC has been waived but after updated DRC system generated a new DRC.
0 p! S0 w. N# F, I0 Z6 V1050918 ALLEGRO_EDITOR MANUFACT Testprep Automatic generate testpoints with wrong padstack Itype in SPB165S026.* V8 Q+ K& |7 s% A& u+ Q8 @# \
1051588 ALLEGRO_EDITOR PAD_EDITOR Pad_Designer library drill report omits some drill holes& T8 i V0 P$ h5 V- E- c: Y& \' D
1052005 SIG_INTEGRITY OTHER Huge difference in Z-Axis delay with the latest hotfix for 16.5 that did not exist in older ISR's of 16.5.
" I# z- R% U1 F1 [: z6 [. D1052045 ALLEGRO_EDITOR OTHER Bug - Thermal relief connects not sustaining 15 degrees component spin in version 16.5 unlike v16.3/ s B. k1 f$ ~& K
1052449 CONCEPT_HDL COPY_PROJECT Copy Project does not update all relative paths in the cpm file. m+ W1 b& \0 |
1052600 ALLEGRO_EDITOR SHAPE Adding a specific cline causing shape errors
" p l3 ]3 L8 ]+ t% F* L' { g/ W* D1052753 ALLEGRO_EDITOR DRC_CONSTR Allegro showing soldermask drc only when the symbol is rotated.
! e5 V4 y b7 N5 W+ n7 _1054235 ALLEGRO_EDITOR PLACEMENT Cannot place alt_symbols for mechanical parts.
" _$ t4 F0 L1 ~, _! W6 ^9 i1054269 ALLEGRO_EDITOR MANUFACT Backdrill Setup and Analysis crashes on attached design
3 z! `" M6 b! A. Z1054351 ALLEGRO_EDITOR SHAPE Shape voiding fails for board having diffpairs with arcs
3 p8 g g1 ]8 Q* ]1054456 ALLEGRO_EDITOR MENTOR mbs2lib incorrectly translates refdes label' c$ u) O: ~: W r% b9 C
1055273 ALLEGRO_EDITOR INTERFACES DXF exported from Allegro has an offset in pad location for Y- direction.
+ k6 |3 b. E2 G4 r# G1055328 CONCEPT_HDL COPY_PROJECT Project Manager - Project Copy
0 _3 u/ L# ^; A& k$ [7 Q1055481 APD SHAPE keepout does not clear shape unless it's picked up and dropped down w7 } g* y8 O& N$ P' H0 L
1055729 CIS GEN_BOM Standard CIS BOM per page is not working correctly with option Process Selection n5 f7 O/ L0 K- }
1056418 ALLEGRO_EDITOR OTHER PDF exports the blank text markers whether or not the markers are visible.4 A5 \* j" |- G1 w- s
1056579 CAPTURE OTHER Ability to define custom variables for titleblocks that update for specific variant views
0 _9 L y* k6 s3 P3 l1057003 ALLEGRO_EDITOR SHAPE Z-copy to create RKI does not follow board outline
& g6 B9 i7 Y9 q1057976 ALLEGRO_EDITOR DRC_CONSTR No Same net Spacing DRC on attached design.: @/ }! u8 S6 }
1058002 SIG_INTEGRITY SIMULATION Incorrect Xtalk sim netlist was created.! Y. ~, D0 `" ]8 D3 c
1058364 ALLEGRO_EDITOR SKILL axlTransformObject() is moving refdes text when only symbol pin is selected for move6 h3 c4 W* |6 Z" o) v
1058940 ALLEGRO_EDITOR INTERFACES IDF(PTC) out command output wrong angle value
# o( G6 O* q2 k% O1059037 CIS PLACE_DATABASE_P What enables the Refresh symbol libs option under hte update menu in CIS explorer/ }* [5 f7 b1 G6 ^
1059389 ALLEGRO_EDITOR MANUFACT about back drill analisys report$ B; U: j# ^/ I( `) G( Z! i
1059901 CONCEPT_HDL CORE Global Property Change and <<OCC_DELETED>> property value.
6 B2 V) j* y' v5 d! k1060428 ADW DESIGN_INIT ADW Flow Manager Copy Project fails to complete
2 p1 F, D$ Q; Y! f1060589 F2B PACKAGERXL Packager Fails with ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance properties.
' `, @3 C5 \' q# L$ L1060977 F2B DESIGNSYNC back annotate in 16.5 does not bring in already placed nets as global nets
% j+ w0 G7 G7 P& Z9 ^1061223 CONCEPT_HDL CHECKPLUS What determines a passthru pin?
7 B2 }4 ~/ N* P3 @- A1061424 CONCEPT_HDL CORE Customer creates <<OCC_DELETED>> property values.
2 ?% R1 g6 V& ~1061572 ALLEGRO_EDITOR INTERACTIV Shortcut keys wont work after "Edit Text" command is finished.( S& {2 P" U3 T @
1061659 ALLEGRO_EDITOR DATABASE Unable to return drawing origin to 00- s9 A* h0 p" `- f; f
1062558 APD DXF_IF If set both in X and Y offset DXF only get one and not get absolutely value in 45 degree rotation
( W. x$ B& d/ E/ M0 C1062982 ALLEGRO_EDITOR MODULES Module containg partitions has been imported to the main design and cant be refreshed.
( p1 M% ~( U, d" N# ` u. r1063284 PCB_LIBRARIAN OTHER PDV Save As is broken4 E, @* |) T+ r8 ^, @
1063658 ALLEGRO_EDITOR SCHEM_FTB Allegro Import Logic does not remove library defined diffpairs
F e5 R4 T' M$ S1063778 CONCEPT_HDL CHECKPLUS The hasSynonyms CheckPlus predicate is not returning true for all global signals.% {! u1 R& Y, a
1063924 CONCEPT_HDL CONSTRAINT_MGR Highlight the net between DE-HDL 16.5 and Constraint Manager.
7 q1 Z& U" N8 j1064707 CONCEPT_HDL CHECKPLUS Rules Checker core dumps on design
' T. M+ w. K- A* ^* V9 M& M1065124 PCB_LIBRARIAN SETUP PTF properties cannot be deleted from the setup in PDV
4 Y+ `8 T4 J& |1 J0 R3 }1065618 CONSTRAINT_MGR ANALYSIS DRCs on board but Constraint Manager shows the columns as green.$ v5 f& s O- Z; }. r
1065641 PCB_LIBRARIAN CORE PDV symbol editor is crashing when deleting a group using delete or CTRL+X, p& l( {) S( L! f; _
1065745 SIP_LAYOUT DATABASE The logic assign net command crashes the application
3 v8 N: ?) f& N& v1065860 ALLEGRO_EDITOR REPORTS Design crashes when running a padstack usage report
& M3 C& F7 V- Y! f; {1066051 ALLEGRO_EDITOR TESTPREP Auto Testprep generation creates TP with Testpoint to Component Locatin DRC3 J, e# r: F& P) V: [
1066318 CONCEPT_HDL CREFER Issue with LOCATION visibility in flattened schematic
; Y+ Z q' J; [1067339 CONSTRAINT_MGR ANALYSIS Relative Propagation Delay analysis in the Partition file seems very inconsitent.9 k1 c# R& o3 K* h. R0 e
1067984 SIP_LAYOUT OTHER layer compare batch fails with write protected file
& t- v( ]! Q& r& P% N+ d1068425 F2B DESIGNVARI Out of memory message in Variant Editor while 縞hange properties� command& B7 _/ h# h$ K! ^( s( n
1068547 ALLEGRO_EDITOR EDIT_ETCH Outward Fanout is not fanning out this 4 sided part as intended% H3 D! h; }9 d: t K0 H- v
1068966 SIP_LAYOUT DRC_CONSTRAINTS DRC update aborts on this design with ERROR -3000067
+ z" D% u( @( F+ y! B* i1069215 CAPTURE DATABASE Capture Crash on usnig a TCL utltiy to correct design
; C6 h% t! g' d" Q1069517 SIP_LAYOUT DIE_EDITOR change die abstract pins tab default action from delete to modify
% I/ m/ n! E! S3 a& M1069915 ALLEGRO_EDITOR EDIT_ETCH Allegro hangs with when doing spread between voids
* p9 L1 n2 n) v/ p7 f' X1070007 ALLEGRO_EDITOR PLOTTING Export IPF omits drill figure characters for backdrill holes$ `5 ^3 s7 r1 o. B! z( m
1071722 SIP_RF DIEEXPORT Virtuoso SiP Architect not writing out pins to the .dra needed for LVS flow
0 Q* R8 {5 S7 Z0 p( y3 }, \7 _- G1072067 APD EXTRACT When expoting using Extracta oblong pads with anyangle are abnormal
& k6 u! X4 d: x( r. V2 t1072791 ALLEGRO_EDITOR DATABASE Database check cannot fix error and keep report the same issues cause artwork cannot export.
/ G6 L5 i; }$ j, g9 I1072806 CIS EXPLORE_DATABASE Query tab in CIS explorer doesn't show searh fields in 16.6
' ^" S9 i9 |0 k$ s2 `1072843 ALLEGRO_EDITOR PLACEMENT The move command that was present in the right mouse pop up menu during manual placement is missing in 16.5
& ^. g/ j3 C ^+ B1072904 SIP_FLOW SIP_LAYOUT Probe pins not being mirrored in Die Editor correctly in Chip Down mode.! T( |3 E& m! Q- G G
1073237 SIG_INTEGRITY GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.7 v& O6 E( @! ?& j& c; U
1073445 ALLEGRO_EDITOR GRAPHICS 'infinite cursor graphics fail -ghost copies as you move cursor
8 |# t S$ S4 O9 p2 G1073464 SCM SCHGEN Schgen never completes.! [- n5 u6 s) a9 e2 p2 {* N
1073587 SIP_LAYOUT OTHER axlSpreadsheetSetWorksheet command clears the cells in memory+ p a' z8 B4 }
1073745 CONCEPT_HDL CORE Import design fails3 H6 W5 X8 d% M+ U
1073852 ALLEGRO_EDITOR INTERACTIV While doing a Copy Via use the last 'Copy Origin'+ J1 p$ k. e$ g! z0 @9 O
1074279 ADW DSN_MIGRATION Design Migration fails purge if there are cells with BODY_TYPE2 f: ?0 {2 p( Z4 w0 |" d+ q9 X) k
1074791 CONCEPT_HDL HDLDIRECT User gets port exists in schematic but not on symbol message even though the port does not exist; z! S& P2 E: Z
1075135 ALLEGRO_EDITOR DRAFTING Ability to edit dimension text block in Instance Parameter
( D6 p6 k) N% Z1075151 ALLEGRO_EDITOR SHAPE Cannot change global shape parameter back to thermal width oversize after having used fixed thermal
6 I/ s- d; q Y, W1075256 ALLEGRO_EDITOR OTHER Import > IPF in 16.5 is dropping data.' t. j+ c/ {; e
1075853 ALLEGRO_EDITOR REPORTS please add "PART_NAME" at Extract UI
$ S7 g( f' L1 R3 |" Z1075934 ALLEGRO_EDITOR DRAFTING Able to Changing Dimension Text Block
+ w! y$ d1 w( B' S5 H& S! G) n# F5 F1075955 CAPTURE SCHEMATIC_EDITOR ZOOM in 16.6 using key "I" on keyboard in not centered on mouse pointer
- Q$ M; M% y. H1075964 ALLEGRO_EDITOR SHAPE Shape voiding is not consistent in conjunction with odd angle and arc traces
5 ?" K0 f _% p0 ^3 r; D+ T1076086 SIP_LAYOUT IMPORT_DATA missing wirebond after import SPD2
* ]1 M' g$ L7 B8 M1076202 ALLEGRO_EDITOR EDIT_ETCH Allegro add connect causing crash after Hotfix) e' c: V! `/ z3 M4 m
1076205 CAPTURE PRINT/PLOT/OUTPU : Printing of User Assigned RefDes
- Y, I* W3 d6 c1076536 ALLEGRO_EDITOR DRC_CONSTR Embedded component which protrude out toward Top do not create DRC with Place Keepout on Top8 t6 Z4 g" R0 B6 ~$ D
1076538 CONCEPT_HDL CORE Property visibility changes in attribute form not updated in schematic canvas.
) [" T1 i0 f) {6 a2 w4 H1076655 APD DXF_IF Dxf does not get offset value if die symbol padstack has offset value
* D/ ^' g+ J+ j1076846 ALLEGRO_EDITOR EDIT_ETCH Grid snapping broken after slide in 16.6
' D; @0 |. c6 G* c1076891 ALLEGRO_EDITOR INTERACTIV Symbol rotation not displayed correctly when defined as a funckey0 v* T1 q) @/ G( R
1076909 ALLEGRO_EDITOR DRC_CONSTR Allegro crashes while placing modules from database
; ^$ @/ V' V3 x1 K* E. u5 ~2 D1077084 CAPTURE NETGROUPS Crash on selecting bus when Enable Global ITC is unset2 k7 [/ E. A6 A( a0 G" ~
1077169 APD SHAPE Shape > Check is producing bogus results.; z) k3 f7 [4 F1 X
1077572 ALLEGRO_EDITOR DATABASE Mechanical symbol created with 16.6 cannot be placed on board./ Q5 f, [( _/ {2 t; `, q( o
1077879 ALLEGRO_EDITOR SKILL Allegro Skill axlDBCreateFilmRec fails when 15th argument missing "draw hole only" for the first tim
9 f" o2 q. [9 ?: c9 Q1078380 SCM OTHER Custom template works in Windows but not Linux
' Z) p& M7 w4 k- _1078497 ALLEGRO_EDITOR INTERFACES Import DXF does not seem to work correctly.1 F5 L. G0 p' S% P$ Y7 Y# q
1078682 ALLEGRO_EDITOR DRC_CONSTR Unaccetable slowness with Slide
# L Z) z* R3 \& {0 d1079082 ALLEGRO_EDITOR PLACEMENT Swap components, gives error SPMHGE-616, when symbols instead of components are selected for swapping
; O% Z* q& \# W& S; ~2 q x* A1079533 ALLEGRO_EDITOR PLACEMENT Swapping components in 16.6 results in Error "E-(SPMHGE-616): Symbol and layer embedding requirements do not match"
4 }; ?; m) k9 P1079937 CAPTURE SCHEMATIC_EDITOR ZOOM in 16.6 is non uniform on text- ?: E% p0 L M/ C6 h& _: f1 Q5 c' U
1082582 ALLEGRO_EDITOR GRAPHICS Allegro hangs on a given testcase using the MMB zoom control) j! ? ? `) l7 Y0 V
1082981 ALLEGRO_EDITOR SKILL Allegro crash while change the new symbol type as mechanical.
& ~. Y2 ^7 t* v8 C4 J4 N' {1083230 SIP_LAYOUT SHAPE Shape fill in 16.6 releaase not fillilng shapes as good as it did in the 16.5 release.! c% ^5 ^- z: F6 s3 w+ i$ H. @, F# V
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发表于 2012-12-17 12:49
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发表于 2012-12-17 16:50
