True-Hspice Device模型参考手册

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Table of Contents
Audience ............................................................................................. iii
Related Documents ............................................................................. iii
Conventions ........................................................................................ iv
' m& O2 S3 [6 zObtaining Customer Support .............................................................. vi
Other Sources of Information ............................................................ vii
& Y! {4 T4 e: YRevision History ............................................................................... viii
Chapter 1 - Overview of Models ..................................................................... 1-1
Using Models to Define Netlist Elements .............................................. 1-2
5 M) z+ j$ g9 T! {$ TSupported Models for Specific Simulators ....................................... 1-2
Selecting Models .............................................................................. 1-3
Example ............................................................................................ 1-3
Chapter 2 - Using Passive Device Models....................................................... 2-1
7 w' ~" }. F8 A# D6 s- H. oResistor Device Model and Equations .................................................... 2-2
Wire RC Model ................................................................................. 2-2
2 d, z- j) X0 S$ m9 \# IResistor Model Equations ................................................................. 2-5
; T/ |3 T4 H3 U: ?( ~+ ]Capacitor Device Model and Equations ............................................... 2-10
Capacitance Model ......................................................................... 2-10
Capacitor Device Equations ........................................................... 2-11
3 B8 n: }# c8 f5 S1 p" @7 e. ZInductor Device Model and Equations ................................................. 2-14
Inductor Core Models ..................................................................... 2-15
Magnetic Core Element Outputs .................................................... 2-18
2 Q. Q, q) a4 QInductor Device Equations ............................................................. 2-19
Jiles-Atherton Ferromagnetic Core Model ..................................... 2-21
: k* r& p, X. Y: kPower Sources ....................................................................................... 2-30
8 Z- `7 W( }, VIndependent Sources ....................................................................... 2-30
  ]& l% g' T6 l9 F: w$ o5 PControlled Sources .......................................................................... 2-33
9 z5 }) C0 @* u+ @Chapter 3 - Using Diodes ................................................................................. 3-1
Diode Types ............................................................................................ 3-2
Using Diode Model Statements .............................................................. 3-3
Setting Control Options .................................................................... 3-3
0 ~9 j( k6 y! `  @/ T8 ^8 a, ~Specifying Junction Diode Models ......................................................... 3-5
5 p. g- d  {9 `Using the Junction Model Statement ................................................ 3-6
' H- t9 p: R8 ^5 e! {9 CUsing Junction Model Parameters .................................................... 3-7
# N' m. {+ @% a- u! I( [Geometric Scaling for Diode Models ............................................. 3-13
1 C; e( i+ G: B8 z. R, xDefining Diode Models ................................................................... 3-15
Determining Temperature Effects on Junction Diodes ................... 3-18
! ?8 j3 t! ^" n" o) {/ T) R" }Using Junction Diode Equations ........................................................... 3-21
Using Junction DC Equations ......................................................... 3-22
- l/ r6 X" V0 P( l* R# h; A8 o4 \Using Diode Capacitance Equations ............................................... 3-25
% F3 c+ d8 K  N# n* oUsing Noise Equations .................................................................... 3-27
Temperature Compensation Equations ........................................... 3-28
' `/ I; ?+ O" t3 K9 h' SUsing the Junction Cap Model .............................................................. 3-32
+ @8 u; v9 R2 {7 [Setting Juncap Model Parameters ................................................... 3-33
Theory ............................................................................................. 3-33
; G2 ~% d. P8 W8 L. E- }JUNCAP Model Equations ............................................................. 3-38
9 d2 O. [" v( l0 p2 a9 PUsing the Fowler-Nordheim Diode ...................................................... 3-46
0 ]9 y( v5 Y/ O  |8 X- T# SConverting National Semiconductor Models ........................................ 3-48
( r$ g4 u% Q; l& CChapter 4 - Using BJT Models ........................................................................ 4-1
Using BJT Models .................................................................................. 4-2
. E4 s+ C, ?7 B1 D2 E8 q5 w9 gSelecting Models ............................................................................... 4-2
% f" _" i! D5 H' @! D; S; }/ UBJT Model Statement ............................................................................. 4-4
& n8 v2 b& ^6 u$ t( e! mUsing BJT Basic Model Parameters ................................................. 4-5
Handling BJT Model Temperature Effects ..................................... 4-15
BJT Device Equivalent Circuits ............................................................ 4-21
: D8 v# f( w: P% ]& p% {2 A# VScaling ............................................................................................. 4-21
5 d7 [. F+ ~( }- b' MUnderstanding the BJT Current Convention ................................... 4-21
Using BJT Equivalent Circuits ....................................................... 4-22
( [- h8 P3 g7 u* }; u, K1 P) BBJT Model Equations (NPN and PNP) ................................................. 4-30
  s" b/ @! U  L5 T4 FUnderstanding Transistor Geometry in Substrate Diodes .............. 4-30
2 r" b+ @/ |; `& u, I+ }+ Y2 zUsing DC Model Equations ............................................................ 4-32
Using Substrate Current Equations ................................................. 4-33
0 g5 b- [5 k# ?# x0 [Using Base Charge Equations ......................................................... 4-34
Using Variable Base Resistance Equations .................................... 4-35
Using BJT Capacitance Equations ........................................................ 4-36
Using Base-Emitter Capacitance Equations ................................... 4-36
Determining Base Collector Capacitance ....................................... 4-38
Using Substrate Capacitance ........................................................... 4-40
Defining BJT Noise Equations ............................................................. 4-42
BJT Temperature Compensation Equations ......................................... 4-44
Using Energy Gap Temperature Equations .................................... 4-44
* w# k1 W) Q/ Z, KSaturation and Beta Temperature Equations, TLEV=0 or 2 ........... 4-44
% U# O4 t7 u1 K! U" c; C5 k( kUsing Saturation and Temperature Equations, TLEV=1 ................ 4-46
Using Saturation Temperature Equations, TLEV=3 ....................... 4-47
Using Capacitance Temperature Equations .................................... 4-49
  K5 Y2 w- E" F& C( I7 U& FParasitic Resistor Temperature Equations ...................................... 4-51
) s! s! P6 R8 \% N) |1 o) `- \5 F, tUsing BJT Level=2 Temperature Equations .................................. 4-52
( |2 `! l' ^3 b+ f8 w2 m6 {BJT Quasi-Saturation Model ................................................................ 4-53
Using Epitaxial Current Source Iepi ............................................... 4-55
Epitaxial Charge Storage Elements Ci and Cx ............................... 4-55
Converting National Semiconductor Models ........................................ 4-58
VBIC Bipolar Transistor Model ........................................................... 4-60
Understanding the History of VBIC ............................................... 4-60
VBIC Parameters ............................................................................ 4-61
Noise Analysis ................................................................................ 4-62
Level 6 Philips Bipolar Model (MEXTRAM Level 503) ..................... 4-71
3 l/ Y0 k" X0 N( X2 pLevel 6 Element Syntax .................................................................. 4-71
Level 6 Model Parameters .............................................................. 4-72
' K+ V5 l5 M; C. I& O; |- FLevel 6 Philips Bipolar Model (MEXTRAM Level 504) ..................... 4-78
Notes ............................................................................................... 4-79
4 e6 m2 |" z, |) h- BLevel 6 Model Parameters (504) ..................................................... 4-80
$ e% M. D9 ?+ ~( E/ ELevel 8 HiCUM Model ......................................................................... 4-94
What is the HiCUM Model? ........................................................... 4-94
HiCUM Model Advantages ............................................................ 4-94
Avant! HiCUM Model vs. Public HiCUM Model .......................... 4-96
+ `, W1 y* @: b# u4 K8 MModel Implementation .................................................................... 4-96
Internal Transistors ......................................................................... 4-97
& h) d$ t% Z1 Z. e7 aLevel 9 VBIC99 Model ...................................................................... 4-110
. f* K3 L8 E: ], G! _Element Syntax of BJT Level 9 .................................................... 4-110
( N+ h) n* M' `5 A$ ZEffects of VBIC99 ........................................................................ 4-112
Model Implementation .................................................................. 4-112
Example ........................................................................................ 4-119
) v8 q. ^# P" p/ u; d" ]6 IVBIC99 Notes for HSPICE Users ................................................ 4-123
3 J# Y9 {% B% s" HLevel 10 Phillips MODELLA Bipolar Model .................................... 4-124
Model Parameters ......................................................................... 4-124
Equivalent Circuits ........................................................................ 4-129
7 }+ C$ T. W. pDC Operating Point Output .......................................................... 4-131
; z" s5 N$ S7 Q9 _Model Equations ........................................................................... 4-132
- k# @, p3 X7 u  t2 Z9 mTemperature Dependence of the Parameters ................................ 4-142
Level 11 UCSD HBT Model .............................................................. 4-146
# n9 @, t4 C4 d8 UUsing the UCSD HBT Model ....................................................... 4-146
+ m) K9 g7 {( p  ^Description of Parameters ............................................................. 4-147
Model Equations ........................................................................... 4-152
4 _9 o, t; M; t. ]3 vEquivalent Circuit ......................................................................... 4-163
. Z( h9 o# O1 }& G7 h4 f  ~Example Avant! True-Hspice Model Statement ........................... 4-165
* d# ]0 J; s9 w& g5 L! aChapter 5 - Using JFET and MESFET Models............................................. 5-1
Understanding JFETs .............................................................................. 5-2
  }6 l5 y; z8 }Specifying a Model ................................................................................. 5-3
Understanding the Capacitor Model ....................................................... 5-5
Model Applications ........................................................................... 5-5
Control Options ................................................................................. 5-6
- H/ N/ V/ _. l) ^+ ]4 |  VJFET and MESFET Equivalent Circuits ................................................. 5-7
& Y) I" w: y+ I1 l7 ^1 SScaling ............................................................................................... 5-7
7 r( m' W/ H( O3 V- Z# t' `. q1 pUnderstanding JFET Current Convention ........................................ 5-7
JFET Equivalent Circuits .................................................................. 5-8
& a( @% `" Q; O4 s+ D, b2 |JFET and MESFET Model Statements ................................................. 5-13
5 q+ M, O) \4 x& ^0 a& H3 F$ ?$ vJFET and MESFET Model Parameters ........................................... 5-13
Gate Diode DC Parameters ............................................................. 5-15
" ]7 @' F" O/ L5 mJFET and MESFET Capacitances ................................................... 5-25
Capacitance Comparison (CAPOP=1 and CAPOP=2) ................... 5-29
! S- Y/ Z- P4 \2 P9 c& N+ BJFET and MESFET DC Equations ................................................. 5-31
JFET and MESFET Noise Models ....................................................... 5-35
3 _, H$ i: Z/ d) z- M$ [1 `Noise Parameters ........................................................................... 5-35
! d4 t9 p/ R. C! z) A, H+ o5 lNoise Equations .............................................................................. 5-35
+ y  N1 Z1 \. }$ BNoise Summary Printout Definitions .............................................. 5-36
& }7 e" u6 ]$ Q' O8 AJFET and MESFET Temperature Equations ........................................ 5-37
. |0 Y6 U3 [2 Q$ t/ n, HTemperature Compensation Equations ........................................... 5-40
! e: Q# l! r1 U) {1 l+ F5 M+ S! ]。。。。。。。。。。。

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