|
|
Fixed CCRs: SPB 17.2 HF0546 q0 v" p; S' n2 E
04-26-20195 j- J+ ?. d& j
========================================================================================================================================================
4 e; _3 C/ A7 k* L4 WCCRID Product ProductLevel2 Title. R0 c& r8 ~ }
========================================================================================================================================================
$ ~; C$ I" b7 A7 g# s! I2060269 ADW DBEDITOR Unable to create ECAD type mixed-case schematic model attributes& A ?2 I+ m6 n' O! a5 q
2030086 ADW LRM Cache part_table.ptf made by LRM Update cannot be read if it has null value in key property
5 @4 P) p9 R h! {! S5 Z1975317 ADW PART_BROWSER Space at the end of line in CDS.LIB results in zero libraries being shown in new component browser# V5 n. }# v, ?2 H! h
2076340 ADW PART_BROWSER .helix folder needs to be deleted for PTF changes to take effect and to convert a design to cache
7 O0 v& H- Q$ Q6 ]& a4 k) x( _2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name" g$ S0 F u+ J" r6 z9 m; g
2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design( f! x' d" b g0 g4 o
2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object
3 U& C; t: a) a2 x5 K0 @2054243 ALLEGRO_EDITOR 3D_CANVAS Plating is not shown on stacked vias in 3D canvas7 E: v. o) f) Q+ B1 p; x7 D3 M
2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation' A) u8 |# \5 Z0 Y& o
2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded! c4 R. t: H7 ~0 Z) w" E
2060489 ALLEGRO_EDITOR COLOR SKILL axlGlobalVisibility() issue in a partition file: VIA/SOLDERMASK_TOP subclass visibility not turned off. F* J& ?" N) E1 |7 S
2072695 ALLEGRO_EDITOR COLOR Clines of colored nets not colored when 'display_nohighlight_priority' is set3 A+ \; M% K* g8 _! a
2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone9 l' X5 i% ^ L! z7 a# B% m" A
2010812 ALLEGRO_EDITOR DATABASE PCB Editor STEP model offsets should follow origin movements
3 J% S2 P+ H7 A) Z2011993 ALLEGRO_EDITOR DATABASE Change STEP model mapping when Symbol Origin is changed in DRA using Setup > Change Drawing Origin
9 W" ]2 X9 @& R9 K6 V5 ?$ w" \2051596 ALLEGRO_EDITOR DATABASE Error for unsupported property in element
9 E& i3 }* e( ^5 J$ s' J( r( Q. P2056497 ALLEGRO_EDITOR DATABASE Place manual is slow p6 `- f M, W- x& [0 R k( H
2059489 ALLEGRO_EDITOR DATABASE DBDOCTOR in batch mode with argument '-check_only' detects text error
2 l& u3 P. e$ G+ s0 z, Y2064268 ALLEGRO_EDITOR DATABASE PCB Editor crashes when running SKILL code
) v0 O, v/ X8 Z: X/ H1 Q) Z1 c+ j4 y2068588 ALLEGRO_EDITOR DATABASE Crash on opening release 16.6 design in 17.2-2016/ d4 ~6 T4 \( B2 l
2079131 ALLEGRO_EDITOR DATABASE axlChangeNet crashes PCB Editor in fast shape mode with Microsoft Visual C++ Runtime Library Error
, }4 K: q% l1 N8 V2034759 ALLEGRO_EDITOR DFM Importing DFT constraints on board does not assign csets to design but shows the csets3 T6 Y7 m, f \9 p9 d$ i( j
2039992 ALLEGRO_EDITOR DFM Cset is not set in Pastemask element of DFA when importing XML Constraint File.1 a1 T) [: u) J. `4 F# }
2046824 ALLEGRO_EDITOR EXTRACT Extracta ECL_NETWORK View reports incorrect pin layer.& p+ n7 b7 q. t! e& v, F
2048912 ALLEGRO_EDITOR IPC Running PCB Design Compare - Graphic mode reports ERROR (SPMHA1-273) 'Shape intersects with itself'
6 {$ q( D( [3 S- u; Y( S0 R5 W2066597 ALLEGRO_EDITOR IPC Graphical compare not completed because of self-intersecting shape locations. e, K; n* q' a* ]) J
2079719 ALLEGRO_EDITOR IPC IPC2581 import fails with error 'Failed to add (LW)POLYLINE'
. ?; q/ q' C: [% a) r. i2066229 ALLEGRO_EDITOR NC Tool code missing in backdrill NC file on choosing 'Optimize Drill Head Travel' in NC Drill
$ r* r4 i0 f: B5 i" r2070379 ALLEGRO_EDITOR NC After running backdrill some vias are shorted to other nets
( I. V! t" |/ h# F( z9 ~1 y2 E2041881 ALLEGRO_EDITOR PAD_EDITOR Difference in locations of drill in pad editor and symbol editor; K& ]' ~$ \& @/ k4 |* p3 l
2058852 ALLEGRO_EDITOR PAD_EDITOR Net associations lost on refreshing vias
v- [# q8 F$ \% N2061580 ALLEGRO_EDITOR PAD_EDITOR Lock Layer Span settings specified in padstack editor not reflected in PCB Editor9 b$ |) K5 o8 A1 }3 Y) w
2048116 ALLEGRO_EDITOR REPORTS Extracta command files not visible in Tools-->Reports when there is a space present in the textpath variable0 [% e u3 q. b- v9 \
2038949 ALLEGRO_EDITOR SCHEM_FTB Netrev is slow if there is an input board file with many modified components
' \, \1 i6 `+ i3 `$ c2052758 ALLEGRO_EDITOR SCHEM_FTB Connectivity objects are being reported as Added and Deleted in Constraint Differences Report
! N, r2 @' H4 }) C+ _/ W1 O2066099 ALLEGRO_EDITOR SCHEM_FTB Inconsistent net names on export physical after changing net names in DE-HDL- w$ i$ h: B- i9 X9 z& j6 O
2043882 ALLEGRO_EDITOR SHAPE Shapes not updated to 'Minimum aperture for gap width' in Global Dynamic Shape Parameters window' ^9 Q1 H! `7 M) B, P( j8 z
2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update
2 e! s2 @- _" B; i: T2052063 ALLEGRO_EDITOR SHAPE Cannot import IPC2581 due to 'Shape intersects with itself': i' G- N6 f+ c- Z; g5 m, k4 h# u
2056478 ALLEGRO_EDITOR SHAPE Editing shape by sliding segment causes PCB Editor to fail due to 0-length segment in shape
# F# l$ K+ k3 x6 {1 D4 P, J2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present
2 }5 m. e0 y5 { }9 G. e7 ~2066473 ALLEGRO_EDITOR SHAPE Teardrops create strange copper shapes; s, C/ F9 W& H; l8 k3 d. u
2079698 ALLEGRO_EDITOR SHAPE IPC2581 import fails with error 'Shapes intersects with itself' q+ ^/ M) C+ ^0 q5 m
2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in HotFix 048.# w# o& `1 i4 i
2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash% Y" N$ F) [7 D6 [/ r# w* f/ i3 O
2023755 ALLEGRO_EDITOR STEP Export STEP includes enclosure even when it is not selected.
$ j. V4 N: i. D. r+ p9 B1881233 ALLEGRO_EDITOR UI_GENERAL Green/white canvas without grid when creating a board file (File - New)
7 Z& d7 r* N. s5 U& u1900525 ALLEGRO_EDITOR UI_GENERAL Resizing the update symbols UI causes the options to overlap and jumble up (refresh issue)
1 r/ d8 E5 q2 T2003861 ALLEGRO_EDITOR UI_GENERAL Same y-coordinate returned for different vertical positions when creating board outline in HotFix 0480 J$ Q& l- `2 T8 R
2033958 ALLEGRO_EDITOR UI_GENERAL Incorrect canvas display on creating a design from the Start page and then opening an existing design
e$ f5 R. `" G6 l2 M% p2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog is behind canvas! j* v: U# l/ G: c
2054429 ALLEGRO_EDITOR UI_GENERAL Editor stops responding until choosing Done after clicking Zoom by Point twice S. y4 J: M% M6 H
2059707 ALLEGRO_EDITOR UI_GENERAL 'HTTPS' links are not shown as hyperlinks when using allegro_html$ @& G( Q7 W# G
2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden, Z# I6 w0 E: K n
2038105 APD DRC_CONSTRAIN APD crashes on update DRC in release 16.6
$ \$ e, N* t4 O2 U" N4 u2050674 APD PARTITION Cannot remove C-Point from a partitioned design* p- m9 ]8 z% u% M- ^) E+ K7 v
2068814 APD WIREBOND Bond wires cross on auto-separate! ]; t1 q9 P+ ~+ l4 o* ~
1967433 CAPTURE OTHER Cannot open DSN or OPJ files by double-clicking if Capture is already open9 w- ?- P# h7 v2 y2 r9 z: D
1967332 CONCEPT_HDL COMP_BROWSER Crash in customer environment on clicking on last row border in PIM after filtering
: x" A" k I# m7 H" b: u" M2001759 CONCEPT_HDL COMP_BROWSER Using Modify Component crashes Design Entry HDL+ R6 a% V' l, L. g J/ v$ W
2020788 CONCEPT_HDL COMP_BROWSER Intermittent crash when clicking bottom edge of part selection table in the Modify Component window( @0 F' u( ]) n' a8 x: g7 [& u
2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved
+ J; f5 f* d3 @$ K% `! o2013002 CONCEPT_HDL CORE Ability to regenerate Netgroup names to remove '_1' suffix
0 b/ ?% m% o- I/ C2026637 CONCEPT_HDL CORE DE-HDL crashing often when launched from EDM Flow Manager
& i5 G! p0 V. w6 {( A2041145 CONCEPT_HDL CORE Set font size & color of netgroup names and netgroup taps
! o" ^) u/ r( {$ G2 t8 m2056743 CONCEPT_HDL CORE NetGroups appended with _1_1, some are empty, and inconsistent in DE-HDL CM and Allegro PCB Editor CM
D- V( W) H p+ k, A& ]0 ?4 v+ z5 X2065889 CONCEPT_HDL CORE DE-HDL Modify command moves location of attached symbol properties) ?# K* G% F6 H+ w# `3 V
2074410 CONCEPT_HDL CORE Full net connectivity not shown in Allegro PCB Editor.) Q+ M, M4 ^4 i( ~8 f5 O) R
2045717 CONCEPT_HDL RF_LAYOUT_DRI The RF PCB Options is greyed out when doing Import Physical on Linux with enterprise licenses
& M! Y4 T) q$ T' S5 k& _2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor' R9 T6 U5 _. _ V
2050521 CONSTRAINT_MGR OTHER Unexpected Xnet removal from schematic when Export to PCB Layout is executed.
$ _7 L, v+ C3 [7 x6 l, ?! t0 j2066270 PCB_LIBRARIAN SYMBOL_EDITOR Unable to edit note text containing comma0 ?5 u9 |% B7 u2 j0 c% X+ |1 {0 {
2069181 PCB_LIBRARIAN SYMBOL_EDITOR Pinlist window expand/collapse buttons act weird first time when invoked.2 ~ |5 a/ ]1 ^1 t; u! |# h9 j
2070007 PCB_LIBRARIAN SYMBOL_EDITOR Project not found error in Symbol Editor when path contains space character9 I5 `# J+ ^! ~/ t* @
2072793 PCB_LIBRARIAN SYMBOL_EDITOR Right-click menu of formatting text objects is not consistent: second and third options are swapped
% F5 g. i5 h; E2073138 PCB_LIBRARIAN SYMBOL_EDITOR New Symbol Editor: Do not allow duplicate properties
2 C7 T" K* \) S3 i ]1957458 PSPICE FRONTENDPLUGI Refresh issue with Bias Display on a new design: bias value not updated0 h5 t5 w+ D9 |% }" `
2022211 PSPICE FRONTENDPLUGI Bias Point results are not updated' i+ o" p. \& M$ _
2031058 PSPICE FRONTENDPLUGI PSpice bias values are not getting updated
) N& g3 [+ A( _! C3 e! r2038021 PSPICE FRONTENDPLUGI Bias display is not updated
0 y! w! _6 ^8 }) ~: T2055274 PSPICE FRONTENDPLUGI Capture crashes on SIMSETUP OK when two projects are open
2 @( k9 d% \0 Q/ @0 s' H: A2053432 RF_PCB OTHER Property on RF component not transferred to new design not containing the component
- \* q; c5 E- a1 P; p: M2003341 SCM SCHGEN Unable to generate a schematic for hierarchical blocks. f' M/ A+ |" |: B* A) _1 ]
2069924 SIP_LAYOUT DIE_ABSTRACT_ Conversion from co-design die to standard die / BGA / anything else must remove floating function pins.
& k8 Y2 v; l& Z* k6 a! a5 e2067894 SIP_LAYOUT OTHER sip database size is enormous for a small component definition used in fdesign
5 |; z T- e; M3 M4 @2067987 SIP_LAYOUT OTHER Orphaned die attachment in SiP Layout cannot be removed
# K V: q' H5 z2072857 SIP_LAYOUT OTHER SiP Layout crashes when using Find by Query and choosing 'Symbols'0 n. |, t/ P' o0 o) X! N# Q2 U6 _
2068973 SIP_LAYOUT REPORTS SiP Layout Missing Fillet report not catching a missing fillet in HotFix 051 and 052
0 S% v0 S0 T" h( a' }8 l2059533 SIP_LAYOUT SYMB_EDIT_APP SiP Layout: Cannot rotate bumps in Symbol Editor application mode4 s: j( O+ Z3 p' I. K3 \
1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error8 D/ C$ {- e; H$ e% c5 f& }$ L6 L* @; m
2054869 SYSTEM_CAPTURE AUTOMATION syscapUtils.tcl command cnsAutoCreateDiffPair is broken due to missing acm_code.il and acm_config.txt files
1 o6 D" g4 I* A& Q( d1966488 SYSTEM_CAPTURE CANVAS_EDIT New folder rename box does not show the text typed.
: R, P" m) x8 i- x" f1814813 SYSTEM_CAPTURE COMPONENT_BRO System Capture session log should specify the CDSSITE path for the current session( u5 e }$ I, G3 I
1977673 SYSTEM_CAPTURE COMPONENT_BRO adding reference blocks through add component error when cell name matches design name
, w1 N. T; N# K+ \2027100 SYSTEM_CAPTURE COMPOSITE_FIL pstdedb.cdsz and netlist preview in System capture is not being updated when individual netlist files are written
+ S6 s e9 }7 Y: F1 L8 D* G1961274 SYSTEM_CAPTURE CONNECTIVITY_ Xnet removed during pin swapping) P, q9 a0 g2 c, X, A- n: e& q. g
2041879 SYSTEM_CAPTURE CONNECTIVITY_ xnets on net with only pull-up resistor
; A6 k" C) n r0 ?$ n5 ?, }; m1889238 SYSTEM_CAPTURE COPY_PASTE Wire fails to connect during copy and paste' G% u0 c5 H ^# E
1993146 SYSTEM_CAPTURE DESIGN_EXPLOR Cannot move page up by only one position5 [1 B/ s' v0 I ]$ S1 j: q
1910941 SYSTEM_CAPTURE MISCELLANEOUS Parts that are not in any schematic page appear in netlsit and BOM" K3 n7 s& I" m5 Z* g: o2 W
1902347 SYSTEM_CAPTURE PRINT Prints all sheets if one sheet is specified as the print range
; h0 U- H) K5 |! b" G0 v; w2041272 SYSTEM_CAPTURE SMART_PDF Smart pdf displays component outline when component is not de-highlighted.
/ w/ v! ]% _# e2065768 SYSTEM_CAPTURE SMART_PDF Custom Variable in Table Object not getting passed to PDF* U+ v) U* p% e" M8 t0 \
1969243 SYSTEM_CAPTURE VARIANT_MANAG Export variant does not name file correctly if the filename contains a space3 r2 B ~+ F/ n, ]/ x, T$ k
1990258 SYSTEM_CAPTURE VARIANT_MANAG Cannot paste copied preferred part to multiple parts with the same part number
* f+ y4 G# [6 B6 i4 a1992250 SYSTEM_CAPTURE WORKSPACE Double-clicking a .CPM file runs System Capture but does not open project |
|
/1 
发表于 2019-5-3 15:45
收藏
淘帖
支持！
反对！
