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Fixed CCRs: SPB 17.2 HF054* v5 K! M7 X3 E: {! f. B4 l
04-26-2019
" V/ e: x4 I Z5 j. N========================================================================================================================================================
! ~; f" r% g9 a0 x/ N5 G xCCRID Product ProductLevel2 Title8 q* C' z1 g0 b1 \0 l v
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2060269 ADW DBEDITOR Unable to create ECAD type mixed-case schematic model attributes
% N. H: ]/ J) f! v2030086 ADW LRM Cache part_table.ptf made by LRM Update cannot be read if it has null value in key property$ c9 h; p" j0 N) j4 e+ K
1975317 ADW PART_BROWSER Space at the end of line in CDS.LIB results in zero libraries being shown in new component browser& w2 W J3 C& D+ v$ A2 }3 y) A
2076340 ADW PART_BROWSER .helix folder needs to be deleted for PTF changes to take effect and to convert a design to cache! R" f6 W5 ~3 r! |
2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name
) M' h& V+ P n- j3 d3 ^2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design% u6 c2 @7 |; J& r4 p5 }
2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object
' P, o6 R6 T1 k1 n2054243 ALLEGRO_EDITOR 3D_CANVAS Plating is not shown on stacked vias in 3D canvas
9 e# U" H) Q/ }+ x& k/ L( }2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation- w& X. @: i z" q9 Q7 C% C- ]
2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded
, k: t, Y4 _ j' I4 ?2 L7 r! r4 `2060489 ALLEGRO_EDITOR COLOR SKILL axlGlobalVisibility() issue in a partition file: VIA/SOLDERMASK_TOP subclass visibility not turned off, L# B' {( {. _" E8 g5 [
2072695 ALLEGRO_EDITOR COLOR Clines of colored nets not colored when 'display_nohighlight_priority' is set
- [' P" n2 M2 P4 X# K9 G& _2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone
8 C. ^- X/ c( x2010812 ALLEGRO_EDITOR DATABASE PCB Editor STEP model offsets should follow origin movements
% k. i/ |$ e( d; z' J2011993 ALLEGRO_EDITOR DATABASE Change STEP model mapping when Symbol Origin is changed in DRA using Setup > Change Drawing Origin
3 ?2 o( ^ s' q' F2051596 ALLEGRO_EDITOR DATABASE Error for unsupported property in element2 ^, p* D$ ^2 f. H f5 F$ ]
2056497 ALLEGRO_EDITOR DATABASE Place manual is slow; r$ H U4 E6 E7 U
2059489 ALLEGRO_EDITOR DATABASE DBDOCTOR in batch mode with argument '-check_only' detects text error( i9 d2 v, b& w2 t& \
2064268 ALLEGRO_EDITOR DATABASE PCB Editor crashes when running SKILL code" n/ s( \8 T; K
2068588 ALLEGRO_EDITOR DATABASE Crash on opening release 16.6 design in 17.2-20168 x$ M- ~2 D5 G3 }% t2 M. c
2079131 ALLEGRO_EDITOR DATABASE axlChangeNet crashes PCB Editor in fast shape mode with Microsoft Visual C++ Runtime Library Error* {2 [/ ^8 o% E1 l; C
2034759 ALLEGRO_EDITOR DFM Importing DFT constraints on board does not assign csets to design but shows the csets
* C8 Q8 W3 p" F2039992 ALLEGRO_EDITOR DFM Cset is not set in Pastemask element of DFA when importing XML Constraint File.$ w5 W/ j2 o/ _7 G2 C/ `7 O
2046824 ALLEGRO_EDITOR EXTRACT Extracta ECL_NETWORK View reports incorrect pin layer.
V6 v+ \/ e8 w& u; L& H$ @# N! k2048912 ALLEGRO_EDITOR IPC Running PCB Design Compare - Graphic mode reports ERROR (SPMHA1-273) 'Shape intersects with itself'
5 Y5 M- h! K; G! e/ V4 c2066597 ALLEGRO_EDITOR IPC Graphical compare not completed because of self-intersecting shape locations5 e* ]4 ]7 B2 H8 j
2079719 ALLEGRO_EDITOR IPC IPC2581 import fails with error 'Failed to add (LW)POLYLINE'8 n5 {2 J( a% R
2066229 ALLEGRO_EDITOR NC Tool code missing in backdrill NC file on choosing 'Optimize Drill Head Travel' in NC Drill; U. U2 b6 c) P9 d$ p( S
2070379 ALLEGRO_EDITOR NC After running backdrill some vias are shorted to other nets4 U+ j' }# X# z. G* u
2041881 ALLEGRO_EDITOR PAD_EDITOR Difference in locations of drill in pad editor and symbol editor) s/ F+ M: L$ v$ e9 Q; z! b
2058852 ALLEGRO_EDITOR PAD_EDITOR Net associations lost on refreshing vias3 {3 t2 ?% U. V7 e
2061580 ALLEGRO_EDITOR PAD_EDITOR Lock Layer Span settings specified in padstack editor not reflected in PCB Editor/ x1 S& L" L, O8 `' h" ?4 j3 e
2048116 ALLEGRO_EDITOR REPORTS Extracta command files not visible in Tools-->Reports when there is a space present in the textpath variable$ i7 x, s$ i2 Z
2038949 ALLEGRO_EDITOR SCHEM_FTB Netrev is slow if there is an input board file with many modified components
. h. V- G/ }" m1 ^! _$ H( Y, L" E/ k2052758 ALLEGRO_EDITOR SCHEM_FTB Connectivity objects are being reported as Added and Deleted in Constraint Differences Report+ C4 ]& Y" R5 g$ e
2066099 ALLEGRO_EDITOR SCHEM_FTB Inconsistent net names on export physical after changing net names in DE-HDL q! \) t9 j2 E7 |; z
2043882 ALLEGRO_EDITOR SHAPE Shapes not updated to 'Minimum aperture for gap width' in Global Dynamic Shape Parameters window4 e4 }0 A) W9 c2 y7 }& P
2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update
! l6 B' f" Q9 M7 |2052063 ALLEGRO_EDITOR SHAPE Cannot import IPC2581 due to 'Shape intersects with itself'
' j7 Z0 G3 C: ^6 w2 d# Z( E$ E6 L* o+ q2056478 ALLEGRO_EDITOR SHAPE Editing shape by sliding segment causes PCB Editor to fail due to 0-length segment in shape0 Z+ b; I4 w* R
2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present4 E/ d) h* F8 ^6 _
2066473 ALLEGRO_EDITOR SHAPE Teardrops create strange copper shapes
9 O6 F9 H8 U% h4 F, b2079698 ALLEGRO_EDITOR SHAPE IPC2581 import fails with error 'Shapes intersects with itself'& C! A" \( }: B. }: Y3 [0 I
2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in HotFix 048.
@8 `9 V& h, B7 V8 r7 F7 A2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash
% k6 S' J+ X [8 y/ z5 O2023755 ALLEGRO_EDITOR STEP Export STEP includes enclosure even when it is not selected.
' V: N, g4 `+ _% L, {6 _8 O5 @6 Q1881233 ALLEGRO_EDITOR UI_GENERAL Green/white canvas without grid when creating a board file (File - New) X' Q2 X5 D: }) N
1900525 ALLEGRO_EDITOR UI_GENERAL Resizing the update symbols UI causes the options to overlap and jumble up (refresh issue)1 E" s* `) f, e2 `+ A1 S$ s/ p
2003861 ALLEGRO_EDITOR UI_GENERAL Same y-coordinate returned for different vertical positions when creating board outline in HotFix 048
" q# a2 c6 J6 N2033958 ALLEGRO_EDITOR UI_GENERAL Incorrect canvas display on creating a design from the Start page and then opening an existing design' ?5 h3 u. M% |; R
2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog is behind canvas' d* w: U: h: k5 \; I7 H
2054429 ALLEGRO_EDITOR UI_GENERAL Editor stops responding until choosing Done after clicking Zoom by Point twice
n" C% d) S# [# t, x- ~% x( l7 s2059707 ALLEGRO_EDITOR UI_GENERAL 'HTTPS' links are not shown as hyperlinks when using allegro_html
! n+ {9 [3 G4 o. v' Z% P2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden
9 {1 C0 |: U' |; z4 b8 ]0 T/ T2038105 APD DRC_CONSTRAIN APD crashes on update DRC in release 16.63 `+ o4 I, L$ C% f$ l$ L3 b0 o
2050674 APD PARTITION Cannot remove C-Point from a partitioned design3 {3 U# v9 i8 m7 _ r T$ |
2068814 APD WIREBOND Bond wires cross on auto-separate$ A& {6 B* g+ e+ u8 S
1967433 CAPTURE OTHER Cannot open DSN or OPJ files by double-clicking if Capture is already open" e5 A$ z% ?3 R' f: ?
1967332 CONCEPT_HDL COMP_BROWSER Crash in customer environment on clicking on last row border in PIM after filtering
& W1 O5 |3 y" Z( z. O! i2001759 CONCEPT_HDL COMP_BROWSER Using Modify Component crashes Design Entry HDL
4 E4 M* v- [8 n+ t4 ]1 s# z1 R; B0 O, E2020788 CONCEPT_HDL COMP_BROWSER Intermittent crash when clicking bottom edge of part selection table in the Modify Component window' C# W1 J$ e( N& X
2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved
7 a) r& A: S6 Y2013002 CONCEPT_HDL CORE Ability to regenerate Netgroup names to remove '_1' suffix% g* L. Y4 w. E
2026637 CONCEPT_HDL CORE DE-HDL crashing often when launched from EDM Flow Manager* c$ Y' h- G8 |; n. \: s
2041145 CONCEPT_HDL CORE Set font size & color of netgroup names and netgroup taps' E" q, q- K0 x1 _
2056743 CONCEPT_HDL CORE NetGroups appended with _1_1, some are empty, and inconsistent in DE-HDL CM and Allegro PCB Editor CM- V0 @ z4 ^4 J4 x. K
2065889 CONCEPT_HDL CORE DE-HDL Modify command moves location of attached symbol properties
4 x/ y; t4 q" `* {- x2074410 CONCEPT_HDL CORE Full net connectivity not shown in Allegro PCB Editor.
9 X, E) A& I( H: Y+ K1 |0 ^% n2045717 CONCEPT_HDL RF_LAYOUT_DRI The RF PCB Options is greyed out when doing Import Physical on Linux with enterprise licenses
6 [6 U1 G6 {8 Z3 v( A& d+ m2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor8 I9 m9 ?- m" p; G: p" r$ H- ^) n9 i
2050521 CONSTRAINT_MGR OTHER Unexpected Xnet removal from schematic when Export to PCB Layout is executed." e( S5 t1 I$ ]7 O2 ]
2066270 PCB_LIBRARIAN SYMBOL_EDITOR Unable to edit note text containing comma' _8 s: i6 D) i. [* F& e6 W
2069181 PCB_LIBRARIAN SYMBOL_EDITOR Pinlist window expand/collapse buttons act weird first time when invoked.
" t. v% s9 \1 S: J( Z, x( R2070007 PCB_LIBRARIAN SYMBOL_EDITOR Project not found error in Symbol Editor when path contains space character
* M- r. c- G9 d2072793 PCB_LIBRARIAN SYMBOL_EDITOR Right-click menu of formatting text objects is not consistent: second and third options are swapped
2 N! \8 k4 N+ }/ p( ~2073138 PCB_LIBRARIAN SYMBOL_EDITOR New Symbol Editor: Do not allow duplicate properties, y" D0 v9 x) ?8 j6 s
1957458 PSPICE FRONTENDPLUGI Refresh issue with Bias Display on a new design: bias value not updated
/ M+ b5 y7 n3 g. }9 b2022211 PSPICE FRONTENDPLUGI Bias Point results are not updated0 M5 l h U# ~, s+ b* b
2031058 PSPICE FRONTENDPLUGI PSpice bias values are not getting updated
* G) ^. `) V6 R$ j, S* ]4 R2038021 PSPICE FRONTENDPLUGI Bias display is not updated, X- D5 L# |! n6 ]
2055274 PSPICE FRONTENDPLUGI Capture crashes on SIMSETUP OK when two projects are open3 y. `# V C) B
2053432 RF_PCB OTHER Property on RF component not transferred to new design not containing the component6 s0 E- z4 k- N- J- b
2003341 SCM SCHGEN Unable to generate a schematic for hierarchical blocks+ g/ l. [3 Q. n ^: y- ^) ?
2069924 SIP_LAYOUT DIE_ABSTRACT_ Conversion from co-design die to standard die / BGA / anything else must remove floating function pins.
# n$ _+ G ~) {1 B4 j) x/ @7 Z2067894 SIP_LAYOUT OTHER sip database size is enormous for a small component definition used in fdesign5 q' R2 S% y* [/ k, c% b+ |# |/ t
2067987 SIP_LAYOUT OTHER Orphaned die attachment in SiP Layout cannot be removed) t, ]9 _) V N: M6 t
2072857 SIP_LAYOUT OTHER SiP Layout crashes when using Find by Query and choosing 'Symbols'6 J8 k& ^$ M/ r
2068973 SIP_LAYOUT REPORTS SiP Layout Missing Fillet report not catching a missing fillet in HotFix 051 and 0528 s' z% q/ T' `, m3 L, a2 L8 {
2059533 SIP_LAYOUT SYMB_EDIT_APP SiP Layout: Cannot rotate bumps in Symbol Editor application mode! l* o- U$ d% q* M- q' Z1 n" Q3 _
1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error J5 I7 `( C7 m+ N6 ]! m) c
2054869 SYSTEM_CAPTURE AUTOMATION syscapUtils.tcl command cnsAutoCreateDiffPair is broken due to missing acm_code.il and acm_config.txt files8 S! Y4 v1 T! V* M* z; e9 T' k
1966488 SYSTEM_CAPTURE CANVAS_EDIT New folder rename box does not show the text typed., g+ T" i& P" |6 T! c
1814813 SYSTEM_CAPTURE COMPONENT_BRO System Capture session log should specify the CDSSITE path for the current session
2 [; W2 f/ K5 h; h3 q* f1 K1977673 SYSTEM_CAPTURE COMPONENT_BRO adding reference blocks through add component error when cell name matches design name
' l7 P9 ~( N5 C5 C2027100 SYSTEM_CAPTURE COMPOSITE_FIL pstdedb.cdsz and netlist preview in System capture is not being updated when individual netlist files are written ]# C* T/ H- g8 L9 S) m* a+ T
1961274 SYSTEM_CAPTURE CONNECTIVITY_ Xnet removed during pin swapping! s c6 F& ]- U$ H" G! }
2041879 SYSTEM_CAPTURE CONNECTIVITY_ xnets on net with only pull-up resistor
' O3 X8 t9 a ?$ I; }1889238 SYSTEM_CAPTURE COPY_PASTE Wire fails to connect during copy and paste
& z- H& ~/ D4 K( O8 L1993146 SYSTEM_CAPTURE DESIGN_EXPLOR Cannot move page up by only one position! |2 V( z! `$ _8 {0 V; ^
1910941 SYSTEM_CAPTURE MISCELLANEOUS Parts that are not in any schematic page appear in netlsit and BOM5 m b4 h. L! ]& E& F
1902347 SYSTEM_CAPTURE PRINT Prints all sheets if one sheet is specified as the print range* | A Z) u+ u# ?
2041272 SYSTEM_CAPTURE SMART_PDF Smart pdf displays component outline when component is not de-highlighted.
8 T7 b% k4 j9 ]; ~3 ?2065768 SYSTEM_CAPTURE SMART_PDF Custom Variable in Table Object not getting passed to PDF
4 s+ F$ c9 g; {! `6 D8 q) F7 |1969243 SYSTEM_CAPTURE VARIANT_MANAG Export variant does not name file correctly if the filename contains a space
( d ~6 X4 i4 U* h, T; F/ }1990258 SYSTEM_CAPTURE VARIANT_MANAG Cannot paste copied preferred part to multiple parts with the same part number# D1 {% E& S2 O( ]7 Y# K+ m( a6 @
1992250 SYSTEM_CAPTURE WORKSPACE Double-clicking a .CPM file runs System Capture but does not open project |
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发表于 2019-5-3 15:45
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