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Fixed CCRs: SPB 17.2 HF0544 B0 B) G' s' s* a- U; ]# W
04-26-2019+ Y( J/ D8 D( H q# b7 \( _* K( M
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( V A; \8 n, hCCRID Product ProductLevel2 Title7 [( F, t) S; j" Z) D8 a9 ?
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2060269 ADW DBEDITOR Unable to create ECAD type mixed-case schematic model attributes0 k+ {5 y. ^7 `" [/ R
2030086 ADW LRM Cache part_table.ptf made by LRM Update cannot be read if it has null value in key property
8 k5 p$ w; |6 G I. k8 D% N7 y1975317 ADW PART_BROWSER Space at the end of line in CDS.LIB results in zero libraries being shown in new component browser) m# _7 C/ F; v: J! M
2076340 ADW PART_BROWSER .helix folder needs to be deleted for PTF changes to take effect and to convert a design to cache) A7 W( C; D$ n% \2 n) X
2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name
" J% J7 l3 I& f( P* t# c% Y- T3 V1 C( E+ h2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design
{. j; ?$ x, e% B/ B3 }2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object- n, j- `+ A# M; Q, A+ C1 P) @
2054243 ALLEGRO_EDITOR 3D_CANVAS Plating is not shown on stacked vias in 3D canvas
7 w6 |3 w# ^3 [8 J- F# j2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation7 z1 E1 ~1 s1 S' {5 `0 n
2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded
8 Y/ F& J- J# \1 B ]5 }2060489 ALLEGRO_EDITOR COLOR SKILL axlGlobalVisibility() issue in a partition file: VIA/SOLDERMASK_TOP subclass visibility not turned off
, M7 R4 i2 l2 K3 [2072695 ALLEGRO_EDITOR COLOR Clines of colored nets not colored when 'display_nohighlight_priority' is set u }& a8 G8 |
2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone
5 n3 v% F+ ]8 P7 h2010812 ALLEGRO_EDITOR DATABASE PCB Editor STEP model offsets should follow origin movements
5 r4 }4 ?$ K' v# u |" w0 k% q2011993 ALLEGRO_EDITOR DATABASE Change STEP model mapping when Symbol Origin is changed in DRA using Setup > Change Drawing Origin
" }( M4 D9 o' d( O0 ]' C2051596 ALLEGRO_EDITOR DATABASE Error for unsupported property in element' s/ a0 Q- v! G, O. O
2056497 ALLEGRO_EDITOR DATABASE Place manual is slow8 d1 g* a5 j0 Y
2059489 ALLEGRO_EDITOR DATABASE DBDOCTOR in batch mode with argument '-check_only' detects text error$ E$ \1 q8 D3 G4 w) c4 T
2064268 ALLEGRO_EDITOR DATABASE PCB Editor crashes when running SKILL code
2 T/ I9 w2 s- u0 l& u* [2068588 ALLEGRO_EDITOR DATABASE Crash on opening release 16.6 design in 17.2-2016
# N# ~' T: p& q& j5 v0 Z# B2079131 ALLEGRO_EDITOR DATABASE axlChangeNet crashes PCB Editor in fast shape mode with Microsoft Visual C++ Runtime Library Error& y5 |, u; |% e5 m2 U
2034759 ALLEGRO_EDITOR DFM Importing DFT constraints on board does not assign csets to design but shows the csets6 M0 Y9 w% y! ?7 d- H# e7 w. h
2039992 ALLEGRO_EDITOR DFM Cset is not set in Pastemask element of DFA when importing XML Constraint File.8 m/ b7 _5 Q& f5 d
2046824 ALLEGRO_EDITOR EXTRACT Extracta ECL_NETWORK View reports incorrect pin layer.. K: `5 r2 x7 H0 R! {
2048912 ALLEGRO_EDITOR IPC Running PCB Design Compare - Graphic mode reports ERROR (SPMHA1-273) 'Shape intersects with itself'' u* {. P, G3 O. o$ Y* [
2066597 ALLEGRO_EDITOR IPC Graphical compare not completed because of self-intersecting shape locations' F# {2 K9 w: ~( C% i
2079719 ALLEGRO_EDITOR IPC IPC2581 import fails with error 'Failed to add (LW)POLYLINE'
$ T! B+ N. O) p# v2066229 ALLEGRO_EDITOR NC Tool code missing in backdrill NC file on choosing 'Optimize Drill Head Travel' in NC Drill$ j6 V5 E4 C: }8 o1 q& G' k1 m6 z. X
2070379 ALLEGRO_EDITOR NC After running backdrill some vias are shorted to other nets
0 e- Q% @; u8 |. v+ ~; ^8 w2041881 ALLEGRO_EDITOR PAD_EDITOR Difference in locations of drill in pad editor and symbol editor! t4 T p, _, f: f' F. h
2058852 ALLEGRO_EDITOR PAD_EDITOR Net associations lost on refreshing vias
, i. N( ~7 O% K" O% c2061580 ALLEGRO_EDITOR PAD_EDITOR Lock Layer Span settings specified in padstack editor not reflected in PCB Editor
" v: j, O9 e2 Q& Y6 B( L; y6 ?2048116 ALLEGRO_EDITOR REPORTS Extracta command files not visible in Tools-->Reports when there is a space present in the textpath variable
6 e3 d' n! j4 \5 {, F i G. I9 T2038949 ALLEGRO_EDITOR SCHEM_FTB Netrev is slow if there is an input board file with many modified components
+ C2 D+ w# D e1 w4 j$ Y2052758 ALLEGRO_EDITOR SCHEM_FTB Connectivity objects are being reported as Added and Deleted in Constraint Differences Report$ {2 s% y1 h; A8 f
2066099 ALLEGRO_EDITOR SCHEM_FTB Inconsistent net names on export physical after changing net names in DE-HDL
8 `& \. _, j. T2043882 ALLEGRO_EDITOR SHAPE Shapes not updated to 'Minimum aperture for gap width' in Global Dynamic Shape Parameters window
/ G$ {, t6 f: @) m2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update
6 H& J G( r' @2052063 ALLEGRO_EDITOR SHAPE Cannot import IPC2581 due to 'Shape intersects with itself'' e- I2 E7 z1 \5 a9 A
2056478 ALLEGRO_EDITOR SHAPE Editing shape by sliding segment causes PCB Editor to fail due to 0-length segment in shape
: G a0 c- u. O- i2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present
1 L, M! r# K/ J4 _! A2066473 ALLEGRO_EDITOR SHAPE Teardrops create strange copper shapes
, q. B' |2 j( `2079698 ALLEGRO_EDITOR SHAPE IPC2581 import fails with error 'Shapes intersects with itself'
6 C" K* g/ k" Q- p: H- @# }% Y. y2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in HotFix 048.
1 a( N1 C. y+ p2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash4 A& H7 |. B5 a
2023755 ALLEGRO_EDITOR STEP Export STEP includes enclosure even when it is not selected.5 A6 I2 s) b) m( t, f
1881233 ALLEGRO_EDITOR UI_GENERAL Green/white canvas without grid when creating a board file (File - New)6 P& [ V( k6 [; m. Z7 t# z
1900525 ALLEGRO_EDITOR UI_GENERAL Resizing the update symbols UI causes the options to overlap and jumble up (refresh issue): v! l9 } I: S$ v' b
2003861 ALLEGRO_EDITOR UI_GENERAL Same y-coordinate returned for different vertical positions when creating board outline in HotFix 048
, f) Q$ o6 r# _0 a' I) Q# r% i' ~2033958 ALLEGRO_EDITOR UI_GENERAL Incorrect canvas display on creating a design from the Start page and then opening an existing design
" I+ \- f0 b7 m ?1 N: k$ e2 U2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog is behind canvas
* g* X+ G. C0 W- H2054429 ALLEGRO_EDITOR UI_GENERAL Editor stops responding until choosing Done after clicking Zoom by Point twice. ^# Z7 m& q8 h
2059707 ALLEGRO_EDITOR UI_GENERAL 'HTTPS' links are not shown as hyperlinks when using allegro_html
; @5 s- j, ?6 i6 ]( W3 k( }& b2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden
, X2 A; @. { m% N5 | D9 ~9 O# _7 P2038105 APD DRC_CONSTRAIN APD crashes on update DRC in release 16.6
9 H* k+ t1 S" h' f- P2050674 APD PARTITION Cannot remove C-Point from a partitioned design
8 L% v9 Y$ D0 `4 G2068814 APD WIREBOND Bond wires cross on auto-separate
4 v2 A+ i' f0 e. Q1967433 CAPTURE OTHER Cannot open DSN or OPJ files by double-clicking if Capture is already open
. L l; B3 a; M1967332 CONCEPT_HDL COMP_BROWSER Crash in customer environment on clicking on last row border in PIM after filtering
- b# }# J9 ~* J( y0 V! y! }- A2001759 CONCEPT_HDL COMP_BROWSER Using Modify Component crashes Design Entry HDL. G$ ~: q6 N& r. M& N
2020788 CONCEPT_HDL COMP_BROWSER Intermittent crash when clicking bottom edge of part selection table in the Modify Component window
; m! H& Q+ F& p. b3 p2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved! }2 T; a3 b8 L. r
2013002 CONCEPT_HDL CORE Ability to regenerate Netgroup names to remove '_1' suffix! @( C4 o6 o8 V, L3 s9 _
2026637 CONCEPT_HDL CORE DE-HDL crashing often when launched from EDM Flow Manager
q) W1 m; k' m6 p* {( m2041145 CONCEPT_HDL CORE Set font size & color of netgroup names and netgroup taps% i9 T$ I4 O% D0 H+ W( z6 N
2056743 CONCEPT_HDL CORE NetGroups appended with _1_1, some are empty, and inconsistent in DE-HDL CM and Allegro PCB Editor CM+ g+ T. j' A8 B# f0 L0 B" k9 V. u& R( k: a4 z
2065889 CONCEPT_HDL CORE DE-HDL Modify command moves location of attached symbol properties
7 A7 V1 S$ t+ I3 T5 h8 y3 B2074410 CONCEPT_HDL CORE Full net connectivity not shown in Allegro PCB Editor.) j+ N; Z9 X) h
2045717 CONCEPT_HDL RF_LAYOUT_DRI The RF PCB Options is greyed out when doing Import Physical on Linux with enterprise licenses
& o( H" O" O2 E& N2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor
8 _/ `2 j* _- [2050521 CONSTRAINT_MGR OTHER Unexpected Xnet removal from schematic when Export to PCB Layout is executed.2 Q$ p8 s# y3 e% c! K/ C1 T+ g( y
2066270 PCB_LIBRARIAN SYMBOL_EDITOR Unable to edit note text containing comma b* v0 q& y4 ?3 H. Q
2069181 PCB_LIBRARIAN SYMBOL_EDITOR Pinlist window expand/collapse buttons act weird first time when invoked.( D) G# S& B7 T! e* \2 b
2070007 PCB_LIBRARIAN SYMBOL_EDITOR Project not found error in Symbol Editor when path contains space character2 a9 Q1 f \ M9 a; r* ?( E( g1 a5 g
2072793 PCB_LIBRARIAN SYMBOL_EDITOR Right-click menu of formatting text objects is not consistent: second and third options are swapped4 }6 ?. s' G3 K' f8 C5 N3 G# k
2073138 PCB_LIBRARIAN SYMBOL_EDITOR New Symbol Editor: Do not allow duplicate properties
7 s$ z) j, \2 g/ Q1957458 PSPICE FRONTENDPLUGI Refresh issue with Bias Display on a new design: bias value not updated
n% x2 M: }6 U: e5 I/ B) C2022211 PSPICE FRONTENDPLUGI Bias Point results are not updated
" X4 g B* M. N- i2031058 PSPICE FRONTENDPLUGI PSpice bias values are not getting updated1 z3 Z N; P4 G: u: M7 }. F7 ~6 _
2038021 PSPICE FRONTENDPLUGI Bias display is not updated0 M6 ], U/ p, L& S% i( c5 M
2055274 PSPICE FRONTENDPLUGI Capture crashes on SIMSETUP OK when two projects are open
5 `( u0 P+ R( \# e2053432 RF_PCB OTHER Property on RF component not transferred to new design not containing the component. \* G/ R9 [ a; L \
2003341 SCM SCHGEN Unable to generate a schematic for hierarchical blocks
. D( {: E& F, E1 x2069924 SIP_LAYOUT DIE_ABSTRACT_ Conversion from co-design die to standard die / BGA / anything else must remove floating function pins.
( L- ]& e. e% ~& n+ l$ A2067894 SIP_LAYOUT OTHER sip database size is enormous for a small component definition used in fdesign. I5 ]8 Q8 v& Z1 v- P' l
2067987 SIP_LAYOUT OTHER Orphaned die attachment in SiP Layout cannot be removed- G. N0 o3 L8 k1 j" S: E# W
2072857 SIP_LAYOUT OTHER SiP Layout crashes when using Find by Query and choosing 'Symbols'9 T+ _) A8 }7 K8 G
2068973 SIP_LAYOUT REPORTS SiP Layout Missing Fillet report not catching a missing fillet in HotFix 051 and 0526 n1 J8 `4 _3 L( V4 h* G
2059533 SIP_LAYOUT SYMB_EDIT_APP SiP Layout: Cannot rotate bumps in Symbol Editor application mode0 B2 B/ y7 g; L0 r
1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error0 b V/ }4 K6 B% b% K
2054869 SYSTEM_CAPTURE AUTOMATION syscapUtils.tcl command cnsAutoCreateDiffPair is broken due to missing acm_code.il and acm_config.txt files% i3 Y/ ?; ]2 K @
1966488 SYSTEM_CAPTURE CANVAS_EDIT New folder rename box does not show the text typed.; ^" Q6 k) v0 x# |5 O6 _8 ^( H
1814813 SYSTEM_CAPTURE COMPONENT_BRO System Capture session log should specify the CDSSITE path for the current session2 T0 L# W, a! I4 v# Y3 X- k
1977673 SYSTEM_CAPTURE COMPONENT_BRO adding reference blocks through add component error when cell name matches design name
& B5 _& q' W0 o* W2 X2 k2027100 SYSTEM_CAPTURE COMPOSITE_FIL pstdedb.cdsz and netlist preview in System capture is not being updated when individual netlist files are written+ M, f' Q9 R, Q2 J
1961274 SYSTEM_CAPTURE CONNECTIVITY_ Xnet removed during pin swapping
$ U. e# s: t# R7 @) [2041879 SYSTEM_CAPTURE CONNECTIVITY_ xnets on net with only pull-up resistor7 }; E" w7 S8 s- J8 g" t- r5 \
1889238 SYSTEM_CAPTURE COPY_PASTE Wire fails to connect during copy and paste
! g2 M9 r C* H8 H. F X1993146 SYSTEM_CAPTURE DESIGN_EXPLOR Cannot move page up by only one position, a& ~1 G: D& B, Q
1910941 SYSTEM_CAPTURE MISCELLANEOUS Parts that are not in any schematic page appear in netlsit and BOM1 t, b$ y( c8 ?: ^
1902347 SYSTEM_CAPTURE PRINT Prints all sheets if one sheet is specified as the print range4 {& _6 \( @5 Y8 y
2041272 SYSTEM_CAPTURE SMART_PDF Smart pdf displays component outline when component is not de-highlighted.9 S( ~( q5 H/ D
2065768 SYSTEM_CAPTURE SMART_PDF Custom Variable in Table Object not getting passed to PDF- n k. S& H* [ C5 u: u" c O
1969243 SYSTEM_CAPTURE VARIANT_MANAG Export variant does not name file correctly if the filename contains a space
! ?& a: J+ ]0 o# i7 C; O1990258 SYSTEM_CAPTURE VARIANT_MANAG Cannot paste copied preferred part to multiple parts with the same part number: L8 Z& k) U5 r3 P- r0 D
1992250 SYSTEM_CAPTURE WORKSPACE Double-clicking a .CPM file runs System Capture but does not open project |
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发表于 2019-5-3 15:45
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