|
|
Fixed CCRs: SPB 17.2 HF054
* R" ?! d6 {8 F04-26-20194 x3 E n7 q/ d) r
========================================================================================================================================================
% o% ^, D9 I4 }; N/ r+ TCCRID Product ProductLevel2 Title
1 o9 E+ y' w/ V8 F========================================================================================================================================================
/ W5 ] P6 _& d+ E. P- O2060269 ADW DBEDITOR Unable to create ECAD type mixed-case schematic model attributes
, b' r% m' p: I, Z9 X9 u, j2030086 ADW LRM Cache part_table.ptf made by LRM Update cannot be read if it has null value in key property$ \/ O3 c, w8 W. M f; C
1975317 ADW PART_BROWSER Space at the end of line in CDS.LIB results in zero libraries being shown in new component browser
- n5 Y! d$ o/ ^; `$ h# F1 |2076340 ADW PART_BROWSER .helix folder needs to be deleted for PTF changes to take effect and to convert a design to cache9 u. J v/ D, u! `5 k2 o
2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name, b4 k) }* w3 Y& s g/ Y8 @$ ~6 I
2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design i3 m6 P1 L( h+ K/ o' @& b
2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object P5 j: v( \) {) }9 N; Y
2054243 ALLEGRO_EDITOR 3D_CANVAS Plating is not shown on stacked vias in 3D canvas
0 L& H# v: ^; Y5 a P) Y2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation
& s+ }3 |, h( m9 L0 c# v2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded) {/ l( M* d9 x/ E
2060489 ALLEGRO_EDITOR COLOR SKILL axlGlobalVisibility() issue in a partition file: VIA/SOLDERMASK_TOP subclass visibility not turned off9 \$ a1 b4 g+ M
2072695 ALLEGRO_EDITOR COLOR Clines of colored nets not colored when 'display_nohighlight_priority' is set h# A/ c! j/ ]
2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone. q0 ~* ]% [4 R' g' S
2010812 ALLEGRO_EDITOR DATABASE PCB Editor STEP model offsets should follow origin movements8 a1 v4 y" ?& D* C# }* l
2011993 ALLEGRO_EDITOR DATABASE Change STEP model mapping when Symbol Origin is changed in DRA using Setup > Change Drawing Origin `: E, A4 {. w
2051596 ALLEGRO_EDITOR DATABASE Error for unsupported property in element3 I& d: ?# {" \4 `2 G9 d. R
2056497 ALLEGRO_EDITOR DATABASE Place manual is slow# N' F% {, Z$ u1 c" n
2059489 ALLEGRO_EDITOR DATABASE DBDOCTOR in batch mode with argument '-check_only' detects text error0 w! I# J) O* v. e$ c% ]- Z
2064268 ALLEGRO_EDITOR DATABASE PCB Editor crashes when running SKILL code
: q" t$ g, w8 O3 W1 {. h2068588 ALLEGRO_EDITOR DATABASE Crash on opening release 16.6 design in 17.2-20165 `' E1 r% P7 J4 s+ E
2079131 ALLEGRO_EDITOR DATABASE axlChangeNet crashes PCB Editor in fast shape mode with Microsoft Visual C++ Runtime Library Error
7 v3 _9 G/ W5 `, d/ K4 Z, S5 d0 h0 ~2034759 ALLEGRO_EDITOR DFM Importing DFT constraints on board does not assign csets to design but shows the csets
7 g, n" ~0 I( H1 v; ^% J2039992 ALLEGRO_EDITOR DFM Cset is not set in Pastemask element of DFA when importing XML Constraint File.
% e' I; P& Y; Z% j2046824 ALLEGRO_EDITOR EXTRACT Extracta ECL_NETWORK View reports incorrect pin layer.+ i7 S3 K) z2 P: m# W, }; b
2048912 ALLEGRO_EDITOR IPC Running PCB Design Compare - Graphic mode reports ERROR (SPMHA1-273) 'Shape intersects with itself'3 d3 w+ z. R) }3 ?; @5 `
2066597 ALLEGRO_EDITOR IPC Graphical compare not completed because of self-intersecting shape locations$ F% y- z. g8 M b) G
2079719 ALLEGRO_EDITOR IPC IPC2581 import fails with error 'Failed to add (LW)POLYLINE'
7 R% b" E8 a A/ M6 ~. A- m" D6 |2066229 ALLEGRO_EDITOR NC Tool code missing in backdrill NC file on choosing 'Optimize Drill Head Travel' in NC Drill
9 {1 v/ f3 G# y, h+ s# _. ^! H2070379 ALLEGRO_EDITOR NC After running backdrill some vias are shorted to other nets
2 Z# L& |$ y7 }/ U2 f6 C W2041881 ALLEGRO_EDITOR PAD_EDITOR Difference in locations of drill in pad editor and symbol editor
$ O$ k& S: ~# |9 x3 Q- _2058852 ALLEGRO_EDITOR PAD_EDITOR Net associations lost on refreshing vias( `4 E9 l% f* C C6 W
2061580 ALLEGRO_EDITOR PAD_EDITOR Lock Layer Span settings specified in padstack editor not reflected in PCB Editor* X2 e; D8 Z+ }5 X% p2 p/ H
2048116 ALLEGRO_EDITOR REPORTS Extracta command files not visible in Tools-->Reports when there is a space present in the textpath variable) ^6 \/ @8 l! p
2038949 ALLEGRO_EDITOR SCHEM_FTB Netrev is slow if there is an input board file with many modified components
; X, R# q3 e9 G2052758 ALLEGRO_EDITOR SCHEM_FTB Connectivity objects are being reported as Added and Deleted in Constraint Differences Report
: N# q6 N2 v* B- K# P5 j( L- G2066099 ALLEGRO_EDITOR SCHEM_FTB Inconsistent net names on export physical after changing net names in DE-HDL
, [& x7 f* x. P0 P0 q2 E) r+ L0 d. W2043882 ALLEGRO_EDITOR SHAPE Shapes not updated to 'Minimum aperture for gap width' in Global Dynamic Shape Parameters window
# X# C- s7 r# c8 i4 S: W; m2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update0 T% X8 l& j& R# k& F* v# a4 w
2052063 ALLEGRO_EDITOR SHAPE Cannot import IPC2581 due to 'Shape intersects with itself'2 f) p9 y$ t4 D2 W/ Q0 m* z- \# f
2056478 ALLEGRO_EDITOR SHAPE Editing shape by sliding segment causes PCB Editor to fail due to 0-length segment in shape
5 _& d) V1 {; o8 ^. p: p2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present/ M# C- C) n8 [
2066473 ALLEGRO_EDITOR SHAPE Teardrops create strange copper shapes
" X( X7 w& Q( d) n- O( s% F3 M2079698 ALLEGRO_EDITOR SHAPE IPC2581 import fails with error 'Shapes intersects with itself'
( }6 G- ]+ g8 A' d$ d' |2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in HotFix 048.
6 u2 U* n& Y8 a, A9 H2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash% D) T, F1 ~' t/ m/ ]9 `$ D/ ]- T
2023755 ALLEGRO_EDITOR STEP Export STEP includes enclosure even when it is not selected.# D( `; _0 }$ K$ r2 ]$ o
1881233 ALLEGRO_EDITOR UI_GENERAL Green/white canvas without grid when creating a board file (File - New)
% D) O3 n9 w k, {; S1900525 ALLEGRO_EDITOR UI_GENERAL Resizing the update symbols UI causes the options to overlap and jumble up (refresh issue)
: B( D2 Q( T+ }: ~7 l3 j6 z2003861 ALLEGRO_EDITOR UI_GENERAL Same y-coordinate returned for different vertical positions when creating board outline in HotFix 048
* i- `. {/ L E. W2033958 ALLEGRO_EDITOR UI_GENERAL Incorrect canvas display on creating a design from the Start page and then opening an existing design, k0 Z# ^, \. H
2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog is behind canvas0 C% i& a6 E0 r* P; U
2054429 ALLEGRO_EDITOR UI_GENERAL Editor stops responding until choosing Done after clicking Zoom by Point twice/ s+ n& G, f1 m
2059707 ALLEGRO_EDITOR UI_GENERAL 'HTTPS' links are not shown as hyperlinks when using allegro_html3 m8 P* c. u0 l9 ]4 z7 s
2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden& @# J9 }! l$ p8 U
2038105 APD DRC_CONSTRAIN APD crashes on update DRC in release 16.69 V1 @7 i% {$ p& T3 k. }9 F7 m
2050674 APD PARTITION Cannot remove C-Point from a partitioned design
* H) b8 `8 k: |' \- ]" v+ d2068814 APD WIREBOND Bond wires cross on auto-separate5 ]/ B+ h7 i- ?7 a: \! W9 c
1967433 CAPTURE OTHER Cannot open DSN or OPJ files by double-clicking if Capture is already open
y0 \$ \8 w8 H2 O, `1967332 CONCEPT_HDL COMP_BROWSER Crash in customer environment on clicking on last row border in PIM after filtering
/ R, Y6 r+ Z5 }( l% i! p7 e- z; e2001759 CONCEPT_HDL COMP_BROWSER Using Modify Component crashes Design Entry HDL- O# H# a M6 r) t$ D5 y
2020788 CONCEPT_HDL COMP_BROWSER Intermittent crash when clicking bottom edge of part selection table in the Modify Component window
6 N9 m/ Z6 D- g Z c2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved& }1 R5 O3 w7 l& n
2013002 CONCEPT_HDL CORE Ability to regenerate Netgroup names to remove '_1' suffix
1 [4 i0 S& Z$ Q7 h2026637 CONCEPT_HDL CORE DE-HDL crashing often when launched from EDM Flow Manager
$ ]5 f0 |1 w2 a+ E+ o' [8 t2041145 CONCEPT_HDL CORE Set font size & color of netgroup names and netgroup taps# s' q7 m/ O! S
2056743 CONCEPT_HDL CORE NetGroups appended with _1_1, some are empty, and inconsistent in DE-HDL CM and Allegro PCB Editor CM& \6 H4 \1 ?' ?* W
2065889 CONCEPT_HDL CORE DE-HDL Modify command moves location of attached symbol properties, E! L# D% j8 ]9 Y1 p1 }
2074410 CONCEPT_HDL CORE Full net connectivity not shown in Allegro PCB Editor.
1 \: U M; u3 [+ X2045717 CONCEPT_HDL RF_LAYOUT_DRI The RF PCB Options is greyed out when doing Import Physical on Linux with enterprise licenses7 ^' d2 J! |+ ?* i4 C
2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor8 T( Y0 D# l2 h8 c$ W
2050521 CONSTRAINT_MGR OTHER Unexpected Xnet removal from schematic when Export to PCB Layout is executed.3 C) S/ L5 n- I- f0 |: y
2066270 PCB_LIBRARIAN SYMBOL_EDITOR Unable to edit note text containing comma' o$ I) `# x; e3 F4 z- H' k
2069181 PCB_LIBRARIAN SYMBOL_EDITOR Pinlist window expand/collapse buttons act weird first time when invoked., f# t$ i8 w( L! q
2070007 PCB_LIBRARIAN SYMBOL_EDITOR Project not found error in Symbol Editor when path contains space character6 Y. l8 k5 p7 s5 ~) n) g" |8 l
2072793 PCB_LIBRARIAN SYMBOL_EDITOR Right-click menu of formatting text objects is not consistent: second and third options are swapped
5 k6 q m" K9 k0 u" c! ?2073138 PCB_LIBRARIAN SYMBOL_EDITOR New Symbol Editor: Do not allow duplicate properties
9 L& V! B5 ?/ [( w) K2 [. Z" ~/ V1957458 PSPICE FRONTENDPLUGI Refresh issue with Bias Display on a new design: bias value not updated
$ R4 U. u9 _) v* B0 [) q9 D2022211 PSPICE FRONTENDPLUGI Bias Point results are not updated) a+ y- P" H6 B8 |4 h8 U. e! u( }/ N
2031058 PSPICE FRONTENDPLUGI PSpice bias values are not getting updated8 h% Q1 K2 j& r
2038021 PSPICE FRONTENDPLUGI Bias display is not updated
. `5 @" l0 m* E0 k, l R2055274 PSPICE FRONTENDPLUGI Capture crashes on SIMSETUP OK when two projects are open
9 n. D6 n0 t# V& Y' p" r7 r2053432 RF_PCB OTHER Property on RF component not transferred to new design not containing the component0 f/ `- a: P4 y" ?9 k' Z+ q
2003341 SCM SCHGEN Unable to generate a schematic for hierarchical blocks
3 E% r6 v2 B& ~! l/ f6 o+ E$ g2069924 SIP_LAYOUT DIE_ABSTRACT_ Conversion from co-design die to standard die / BGA / anything else must remove floating function pins." n D: r( R7 Q1 R+ j! E, e8 v
2067894 SIP_LAYOUT OTHER sip database size is enormous for a small component definition used in fdesign3 e: [' A# R5 R
2067987 SIP_LAYOUT OTHER Orphaned die attachment in SiP Layout cannot be removed3 {* }: j3 [! k) m2 i: ^9 D. |4 ^. O
2072857 SIP_LAYOUT OTHER SiP Layout crashes when using Find by Query and choosing 'Symbols'
+ h0 q! S* Q4 u2 l0 ^0 }" A! j) P5 i2068973 SIP_LAYOUT REPORTS SiP Layout Missing Fillet report not catching a missing fillet in HotFix 051 and 052, b: v a7 q- H$ Z
2059533 SIP_LAYOUT SYMB_EDIT_APP SiP Layout: Cannot rotate bumps in Symbol Editor application mode, w6 A4 n* O b T
1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error
+ A6 V% v7 w+ P( p/ Y2054869 SYSTEM_CAPTURE AUTOMATION syscapUtils.tcl command cnsAutoCreateDiffPair is broken due to missing acm_code.il and acm_config.txt files
" \/ q0 ^' z: Y3 R1 Y! o1966488 SYSTEM_CAPTURE CANVAS_EDIT New folder rename box does not show the text typed.2 K5 Y; a! j* q2 @4 p+ ^
1814813 SYSTEM_CAPTURE COMPONENT_BRO System Capture session log should specify the CDSSITE path for the current session
# S7 }6 X3 K/ W- P7 N: z( u1977673 SYSTEM_CAPTURE COMPONENT_BRO adding reference blocks through add component error when cell name matches design name# W4 P: R4 i2 P
2027100 SYSTEM_CAPTURE COMPOSITE_FIL pstdedb.cdsz and netlist preview in System capture is not being updated when individual netlist files are written
' b# t/ b+ _8 X% E1961274 SYSTEM_CAPTURE CONNECTIVITY_ Xnet removed during pin swapping ?1 W1 Y8 O7 C7 d- B$ U8 x2 d) X
2041879 SYSTEM_CAPTURE CONNECTIVITY_ xnets on net with only pull-up resistor6 y# x! W( ]# S* }! M$ P s
1889238 SYSTEM_CAPTURE COPY_PASTE Wire fails to connect during copy and paste
' X+ ~) X5 J. H7 b- }4 W1993146 SYSTEM_CAPTURE DESIGN_EXPLOR Cannot move page up by only one position
: R2 w( r' V. g. \1910941 SYSTEM_CAPTURE MISCELLANEOUS Parts that are not in any schematic page appear in netlsit and BOM
" v. D% V3 C# s+ W1902347 SYSTEM_CAPTURE PRINT Prints all sheets if one sheet is specified as the print range. }5 I2 w* t( _# E. B
2041272 SYSTEM_CAPTURE SMART_PDF Smart pdf displays component outline when component is not de-highlighted./ I+ C+ ~: [8 F
2065768 SYSTEM_CAPTURE SMART_PDF Custom Variable in Table Object not getting passed to PDF
: X' d# h2 ?$ D: Q5 I$ C1969243 SYSTEM_CAPTURE VARIANT_MANAG Export variant does not name file correctly if the filename contains a space/ R6 f& P r; ]! G H9 L
1990258 SYSTEM_CAPTURE VARIANT_MANAG Cannot paste copied preferred part to multiple parts with the same part number/ y# q/ M5 T, A8 Q
1992250 SYSTEM_CAPTURE WORKSPACE Double-clicking a .CPM file runs System Capture but does not open project |
|
/1 
发表于 2019-5-3 15:45
收藏
淘帖
支持！
反对！
