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Fixed CCRs: SPB 17.2 HF054: I5 c* K: S$ R3 m" D
04-26-2019
& s0 G! [/ X- V! c: @; v% y( o7 q========================================================================================================================================================
0 i' L- E) T- ?! {) @" p; XCCRID Product ProductLevel2 Title3 Z( J4 l _6 ^, E% h& `
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2060269 ADW DBEDITOR Unable to create ECAD type mixed-case schematic model attributes7 Z0 ]8 q, [5 \9 v
2030086 ADW LRM Cache part_table.ptf made by LRM Update cannot be read if it has null value in key property9 f) Z% d- v/ @" Y
1975317 ADW PART_BROWSER Space at the end of line in CDS.LIB results in zero libraries being shown in new component browser' h: x) t c0 B" ?" q' }) @* J( @
2076340 ADW PART_BROWSER .helix folder needs to be deleted for PTF changes to take effect and to convert a design to cache
t1 }! t. N$ |7 Q* m( ^2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name
1 ^& l2 ]: E% ?2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design* p" d s6 K2 f
2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object3 l) o, t# U! M V \& s
2054243 ALLEGRO_EDITOR 3D_CANVAS Plating is not shown on stacked vias in 3D canvas
" T2 I, f8 v- O& M6 F4 N2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation$ t: k4 E- o! j; T" q8 T
2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded0 F7 d! @# k" `8 d# j1 l# V' P3 ?
2060489 ALLEGRO_EDITOR COLOR SKILL axlGlobalVisibility() issue in a partition file: VIA/SOLDERMASK_TOP subclass visibility not turned off- ~# t' B5 c, g! s# v
2072695 ALLEGRO_EDITOR COLOR Clines of colored nets not colored when 'display_nohighlight_priority' is set3 ^9 l& |, C0 a
2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone
1 f; ~; r) L" P# B" J0 y) j$ @& W2010812 ALLEGRO_EDITOR DATABASE PCB Editor STEP model offsets should follow origin movements2 q5 d3 T% h! U7 D6 O
2011993 ALLEGRO_EDITOR DATABASE Change STEP model mapping when Symbol Origin is changed in DRA using Setup > Change Drawing Origin
2 J* f$ v. y( H2051596 ALLEGRO_EDITOR DATABASE Error for unsupported property in element
3 g4 L$ ?" H6 Y/ j/ b1 S2 n2056497 ALLEGRO_EDITOR DATABASE Place manual is slow. L! y0 Z9 u7 l [) @+ e; c8 X2 i4 Q8 N
2059489 ALLEGRO_EDITOR DATABASE DBDOCTOR in batch mode with argument '-check_only' detects text error+ ^2 T% U6 ?7 ]( t% S1 S) ~! p
2064268 ALLEGRO_EDITOR DATABASE PCB Editor crashes when running SKILL code- d7 A- c/ @+ i9 i
2068588 ALLEGRO_EDITOR DATABASE Crash on opening release 16.6 design in 17.2-20168 d8 s# q& |4 Z+ J2 o- S
2079131 ALLEGRO_EDITOR DATABASE axlChangeNet crashes PCB Editor in fast shape mode with Microsoft Visual C++ Runtime Library Error2 z) x. F, N) |3 ^# }* G
2034759 ALLEGRO_EDITOR DFM Importing DFT constraints on board does not assign csets to design but shows the csets
+ c% v4 ]; E2 w7 o( I% _2039992 ALLEGRO_EDITOR DFM Cset is not set in Pastemask element of DFA when importing XML Constraint File.0 {6 d; ], t" O+ t% M
2046824 ALLEGRO_EDITOR EXTRACT Extracta ECL_NETWORK View reports incorrect pin layer.4 \* n! f4 R( z: _( R
2048912 ALLEGRO_EDITOR IPC Running PCB Design Compare - Graphic mode reports ERROR (SPMHA1-273) 'Shape intersects with itself'
6 S; H3 S V2 X- a3 j2066597 ALLEGRO_EDITOR IPC Graphical compare not completed because of self-intersecting shape locations/ g) e& _$ f/ X# F/ @) z! y
2079719 ALLEGRO_EDITOR IPC IPC2581 import fails with error 'Failed to add (LW)POLYLINE'( D: Z( U- A$ w1 x) b. H% y
2066229 ALLEGRO_EDITOR NC Tool code missing in backdrill NC file on choosing 'Optimize Drill Head Travel' in NC Drill
1 |( t; f3 d- [( c7 w5 T7 O2070379 ALLEGRO_EDITOR NC After running backdrill some vias are shorted to other nets
. s2 R( _, b1 B. }8 V" A2041881 ALLEGRO_EDITOR PAD_EDITOR Difference in locations of drill in pad editor and symbol editor
- ^8 S# l+ [2 P6 [2058852 ALLEGRO_EDITOR PAD_EDITOR Net associations lost on refreshing vias& n# g0 _% x" `9 R/ {- ]% K1 M1 r9 H+ Q
2061580 ALLEGRO_EDITOR PAD_EDITOR Lock Layer Span settings specified in padstack editor not reflected in PCB Editor8 J. s4 d, t$ P# S
2048116 ALLEGRO_EDITOR REPORTS Extracta command files not visible in Tools-->Reports when there is a space present in the textpath variable
8 L2 l: i7 Q N0 G9 U& P7 {! o2038949 ALLEGRO_EDITOR SCHEM_FTB Netrev is slow if there is an input board file with many modified components
) N/ q( j# \; J2052758 ALLEGRO_EDITOR SCHEM_FTB Connectivity objects are being reported as Added and Deleted in Constraint Differences Report0 d$ ^( n9 w6 }, E
2066099 ALLEGRO_EDITOR SCHEM_FTB Inconsistent net names on export physical after changing net names in DE-HDL
5 C( u9 t3 W" K/ j$ Y' H# t4 z3 Z2043882 ALLEGRO_EDITOR SHAPE Shapes not updated to 'Minimum aperture for gap width' in Global Dynamic Shape Parameters window
, u4 ?+ d1 |9 T, `; U/ S2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update
5 P( |. K6 R- |# `" ~2052063 ALLEGRO_EDITOR SHAPE Cannot import IPC2581 due to 'Shape intersects with itself'7 j, Z5 j' ?# c/ X% C' R
2056478 ALLEGRO_EDITOR SHAPE Editing shape by sliding segment causes PCB Editor to fail due to 0-length segment in shape5 `/ ]0 ?* C% h: l& t7 w3 W
2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present) _7 f& ~# K- I+ y9 E7 p2 M
2066473 ALLEGRO_EDITOR SHAPE Teardrops create strange copper shapes
$ u; D2 |3 K3 ?5 t& b2079698 ALLEGRO_EDITOR SHAPE IPC2581 import fails with error 'Shapes intersects with itself'/ f% X. l3 g" P$ {7 p6 p4 I
2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in HotFix 048.3 L/ C4 L" z9 E, ?& z
2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash
+ P7 G& k3 q2 k' v( j2023755 ALLEGRO_EDITOR STEP Export STEP includes enclosure even when it is not selected.
8 T# Q {& @- |5 Q; t6 t1881233 ALLEGRO_EDITOR UI_GENERAL Green/white canvas without grid when creating a board file (File - New); e0 w- [' g* M$ m- d; k
1900525 ALLEGRO_EDITOR UI_GENERAL Resizing the update symbols UI causes the options to overlap and jumble up (refresh issue)
$ r/ E5 ?+ V: h: j# X2003861 ALLEGRO_EDITOR UI_GENERAL Same y-coordinate returned for different vertical positions when creating board outline in HotFix 048
9 a; d6 ^* z, J" {+ j( k2033958 ALLEGRO_EDITOR UI_GENERAL Incorrect canvas display on creating a design from the Start page and then opening an existing design
4 u' W, c( [, J( Z# t! O! J2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog is behind canvas
. N% P& c& s2 E8 y/ r" y" |2054429 ALLEGRO_EDITOR UI_GENERAL Editor stops responding until choosing Done after clicking Zoom by Point twice; n" w( N# V8 S1 W6 W" H
2059707 ALLEGRO_EDITOR UI_GENERAL 'HTTPS' links are not shown as hyperlinks when using allegro_html7 [6 s2 M7 `' |' T, F- E. \7 ]- B+ [
2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden
) n. F G; w, v, g2038105 APD DRC_CONSTRAIN APD crashes on update DRC in release 16.6
/ F' k @/ j' ~$ u2050674 APD PARTITION Cannot remove C-Point from a partitioned design
6 v/ ]5 g, O2 Z/ ^# d& F* w9 j2068814 APD WIREBOND Bond wires cross on auto-separate
3 }' A3 I$ z, G5 I2 |1967433 CAPTURE OTHER Cannot open DSN or OPJ files by double-clicking if Capture is already open
: a# U6 s$ i' j1 u3 Q) E# E9 {1967332 CONCEPT_HDL COMP_BROWSER Crash in customer environment on clicking on last row border in PIM after filtering* X5 B$ H- B8 G- D, e8 q# U$ t
2001759 CONCEPT_HDL COMP_BROWSER Using Modify Component crashes Design Entry HDL9 F. k8 H; p/ D( v& V
2020788 CONCEPT_HDL COMP_BROWSER Intermittent crash when clicking bottom edge of part selection table in the Modify Component window
; I: {7 h4 {5 T6 ^1 w V2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved. }" C7 A. g" `8 D$ q
2013002 CONCEPT_HDL CORE Ability to regenerate Netgroup names to remove '_1' suffix! P9 l3 m: U% Q1 s* I0 ?0 u
2026637 CONCEPT_HDL CORE DE-HDL crashing often when launched from EDM Flow Manager
2 F: A" F' }5 v, ~5 v Q2041145 CONCEPT_HDL CORE Set font size & color of netgroup names and netgroup taps
- n1 c/ i) Y9 v2 j2056743 CONCEPT_HDL CORE NetGroups appended with _1_1, some are empty, and inconsistent in DE-HDL CM and Allegro PCB Editor CM
" O3 F# G6 Q& y& z% C2 _" r3 x" G. ~2065889 CONCEPT_HDL CORE DE-HDL Modify command moves location of attached symbol properties5 u* k2 a; Y+ G8 S$ V' i8 L5 N
2074410 CONCEPT_HDL CORE Full net connectivity not shown in Allegro PCB Editor.9 R& u& e" J+ L. @( k5 ^
2045717 CONCEPT_HDL RF_LAYOUT_DRI The RF PCB Options is greyed out when doing Import Physical on Linux with enterprise licenses' I q* Q j* R3 A' ^1 F/ ~
2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor& Q5 V( ?8 n6 J: [1 ^1 g5 p
2050521 CONSTRAINT_MGR OTHER Unexpected Xnet removal from schematic when Export to PCB Layout is executed." S. i. d$ {9 ^9 O, I
2066270 PCB_LIBRARIAN SYMBOL_EDITOR Unable to edit note text containing comma
0 G; k9 N" i. s1 K2069181 PCB_LIBRARIAN SYMBOL_EDITOR Pinlist window expand/collapse buttons act weird first time when invoked.
3 T$ J* j9 E; |6 \) D2070007 PCB_LIBRARIAN SYMBOL_EDITOR Project not found error in Symbol Editor when path contains space character9 I* ?! o, M% c3 d7 a: f
2072793 PCB_LIBRARIAN SYMBOL_EDITOR Right-click menu of formatting text objects is not consistent: second and third options are swapped; X9 b# B5 ]! X. c
2073138 PCB_LIBRARIAN SYMBOL_EDITOR New Symbol Editor: Do not allow duplicate properties0 ]! }7 e1 K0 [1 M8 E2 B
1957458 PSPICE FRONTENDPLUGI Refresh issue with Bias Display on a new design: bias value not updated
% F2 E$ k/ F; A" y+ o* q* Q2022211 PSPICE FRONTENDPLUGI Bias Point results are not updated
W9 |+ B$ r/ G9 a& m; @. J2031058 PSPICE FRONTENDPLUGI PSpice bias values are not getting updated" Y( [5 G7 R* ]7 E1 u7 w# G$ A
2038021 PSPICE FRONTENDPLUGI Bias display is not updated
2 V! `9 w2 L& q* J( R2055274 PSPICE FRONTENDPLUGI Capture crashes on SIMSETUP OK when two projects are open
, ?4 h6 n' @6 f3 o7 k& A1 y2053432 RF_PCB OTHER Property on RF component not transferred to new design not containing the component$ [% q- O$ r1 @+ `. k7 F- A
2003341 SCM SCHGEN Unable to generate a schematic for hierarchical blocks5 H# ]( h# U" O! l6 Y1 |
2069924 SIP_LAYOUT DIE_ABSTRACT_ Conversion from co-design die to standard die / BGA / anything else must remove floating function pins.
0 l2 |" e# ^# f. Q. {, Z9 R* l2067894 SIP_LAYOUT OTHER sip database size is enormous for a small component definition used in fdesign
8 `6 q! m8 S# H% j. v& g+ M2067987 SIP_LAYOUT OTHER Orphaned die attachment in SiP Layout cannot be removed
- Z+ x; |/ H* ^4 O0 ^2072857 SIP_LAYOUT OTHER SiP Layout crashes when using Find by Query and choosing 'Symbols'+ _4 h: I9 C( g3 B5 Q
2068973 SIP_LAYOUT REPORTS SiP Layout Missing Fillet report not catching a missing fillet in HotFix 051 and 052" c8 W( j; W+ x# G; G/ e" z
2059533 SIP_LAYOUT SYMB_EDIT_APP SiP Layout: Cannot rotate bumps in Symbol Editor application mode
+ x1 T# ]) s8 M1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error
. ?2 n% b7 N) `* B* r: P2054869 SYSTEM_CAPTURE AUTOMATION syscapUtils.tcl command cnsAutoCreateDiffPair is broken due to missing acm_code.il and acm_config.txt files
) k' \ ~/ O' x! P- w R1966488 SYSTEM_CAPTURE CANVAS_EDIT New folder rename box does not show the text typed.) q) W( y/ F$ C3 J. n" ~5 x
1814813 SYSTEM_CAPTURE COMPONENT_BRO System Capture session log should specify the CDSSITE path for the current session) i" N t# D' S0 d' \2 a
1977673 SYSTEM_CAPTURE COMPONENT_BRO adding reference blocks through add component error when cell name matches design name9 q& T" Z0 B! M" ]" i6 v( S& I
2027100 SYSTEM_CAPTURE COMPOSITE_FIL pstdedb.cdsz and netlist preview in System capture is not being updated when individual netlist files are written3 i' q# H$ S2 e3 j, k" \0 f
1961274 SYSTEM_CAPTURE CONNECTIVITY_ Xnet removed during pin swapping
. i/ N9 l7 S3 e4 ^2041879 SYSTEM_CAPTURE CONNECTIVITY_ xnets on net with only pull-up resistor f4 z* F5 n' w, F
1889238 SYSTEM_CAPTURE COPY_PASTE Wire fails to connect during copy and paste
8 F' m# }9 q$ |1 _; C- k( M1993146 SYSTEM_CAPTURE DESIGN_EXPLOR Cannot move page up by only one position/ _" u8 h- t7 C+ Q7 N
1910941 SYSTEM_CAPTURE MISCELLANEOUS Parts that are not in any schematic page appear in netlsit and BOM
& w M& M9 @/ Y: u6 p/ K" z1902347 SYSTEM_CAPTURE PRINT Prints all sheets if one sheet is specified as the print range
# w' e, W# e3 v) g% I2041272 SYSTEM_CAPTURE SMART_PDF Smart pdf displays component outline when component is not de-highlighted.
% A; R, Z! v$ q& v0 }, z2065768 SYSTEM_CAPTURE SMART_PDF Custom Variable in Table Object not getting passed to PDF% n7 j- T# \) ?3 m! d1 A! x5 i) F
1969243 SYSTEM_CAPTURE VARIANT_MANAG Export variant does not name file correctly if the filename contains a space
. x8 \0 F) s5 g! `7 K1990258 SYSTEM_CAPTURE VARIANT_MANAG Cannot paste copied preferred part to multiple parts with the same part number
+ m- c9 _) e! k! |+ N: u5 r" \' \0 j1992250 SYSTEM_CAPTURE WORKSPACE Double-clicking a .CPM file runs System Capture but does not open project |
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