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Fixed CCRs: SPB 17.2 HF0542 @( k$ j0 X2 G5 ]
04-26-2019
& H. c$ h5 x$ ?, B. D% Y3 m- v========================================================================================================================================================
. A4 V7 _" d: l" S9 g9 C& tCCRID Product ProductLevel2 Title
2 C- b( Q1 O& z. V# F9 _9 O1 e========================================================================================================================================================: j( a, Y! @: m9 s: Q% R8 }9 ?
2060269 ADW DBEDITOR Unable to create ECAD type mixed-case schematic model attributes7 _5 t9 I& I$ E$ Q D# }
2030086 ADW LRM Cache part_table.ptf made by LRM Update cannot be read if it has null value in key property
! g$ @# y5 D: Z* x) W1975317 ADW PART_BROWSER Space at the end of line in CDS.LIB results in zero libraries being shown in new component browser* H' W! Q) s3 K, R
2076340 ADW PART_BROWSER .helix folder needs to be deleted for PTF changes to take effect and to convert a design to cache
, e$ O+ `! d' O2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name1 [# g- b. C( m; o
2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design, N3 { y' ?6 K) f9 [# [
2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object" G) o" G6 y3 H' \2 Q3 E1 m+ m
2054243 ALLEGRO_EDITOR 3D_CANVAS Plating is not shown on stacked vias in 3D canvas, ^* b1 e: I+ s) _( B( U' u
2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation, R" J- p2 f7 x5 F
2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded
& S2 y! x1 r. h2060489 ALLEGRO_EDITOR COLOR SKILL axlGlobalVisibility() issue in a partition file: VIA/SOLDERMASK_TOP subclass visibility not turned off
. i7 B! p# ~, d$ B9 O) V2072695 ALLEGRO_EDITOR COLOR Clines of colored nets not colored when 'display_nohighlight_priority' is set, C* u6 T: i; P* ?: {" y
2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone" p0 c) z& D1 v
2010812 ALLEGRO_EDITOR DATABASE PCB Editor STEP model offsets should follow origin movements
- Q" Z- t' t$ q1 ]- l2011993 ALLEGRO_EDITOR DATABASE Change STEP model mapping when Symbol Origin is changed in DRA using Setup > Change Drawing Origin
+ ~( Y+ H. ], u% y [2051596 ALLEGRO_EDITOR DATABASE Error for unsupported property in element
O$ w! q* T5 N6 W) W6 o2056497 ALLEGRO_EDITOR DATABASE Place manual is slow
. t' _5 C) r0 K0 G. C2059489 ALLEGRO_EDITOR DATABASE DBDOCTOR in batch mode with argument '-check_only' detects text error
$ i2 C* g# G2 C5 M+ D. K/ O2064268 ALLEGRO_EDITOR DATABASE PCB Editor crashes when running SKILL code
; a& W+ t. U" U, C2068588 ALLEGRO_EDITOR DATABASE Crash on opening release 16.6 design in 17.2-2016
3 D$ k, @1 p/ {5 c' Z; k7 B2079131 ALLEGRO_EDITOR DATABASE axlChangeNet crashes PCB Editor in fast shape mode with Microsoft Visual C++ Runtime Library Error
2 H- Q& R' C6 K2034759 ALLEGRO_EDITOR DFM Importing DFT constraints on board does not assign csets to design but shows the csets
* h; ]9 d6 {6 _! E# R2039992 ALLEGRO_EDITOR DFM Cset is not set in Pastemask element of DFA when importing XML Constraint File.
7 c: k: D* j' _9 R2046824 ALLEGRO_EDITOR EXTRACT Extracta ECL_NETWORK View reports incorrect pin layer. c2 n q8 @8 o5 v
2048912 ALLEGRO_EDITOR IPC Running PCB Design Compare - Graphic mode reports ERROR (SPMHA1-273) 'Shape intersects with itself' I+ K& N+ |. L( r
2066597 ALLEGRO_EDITOR IPC Graphical compare not completed because of self-intersecting shape locations! R. ]# O1 z/ [8 y. {
2079719 ALLEGRO_EDITOR IPC IPC2581 import fails with error 'Failed to add (LW)POLYLINE'/ R, J$ `, l+ w; N" O8 Z+ j
2066229 ALLEGRO_EDITOR NC Tool code missing in backdrill NC file on choosing 'Optimize Drill Head Travel' in NC Drill
. ^/ H. x) b9 z- v& o$ C2070379 ALLEGRO_EDITOR NC After running backdrill some vias are shorted to other nets( D; A8 S6 b2 j+ J
2041881 ALLEGRO_EDITOR PAD_EDITOR Difference in locations of drill in pad editor and symbol editor
7 {) h5 C8 w3 E! K/ L2058852 ALLEGRO_EDITOR PAD_EDITOR Net associations lost on refreshing vias
* T' p6 R0 {9 K6 G0 y1 M0 X( S2061580 ALLEGRO_EDITOR PAD_EDITOR Lock Layer Span settings specified in padstack editor not reflected in PCB Editor
' p& ^# e M7 u1 @ ?$ b2048116 ALLEGRO_EDITOR REPORTS Extracta command files not visible in Tools-->Reports when there is a space present in the textpath variable+ Y7 o( s+ L$ y1 L
2038949 ALLEGRO_EDITOR SCHEM_FTB Netrev is slow if there is an input board file with many modified components
7 f# I; a0 j% B- a; w) o5 t/ D2052758 ALLEGRO_EDITOR SCHEM_FTB Connectivity objects are being reported as Added and Deleted in Constraint Differences Report
+ h; N# `: b* D' [3 W* Z$ [8 P- x& ?2066099 ALLEGRO_EDITOR SCHEM_FTB Inconsistent net names on export physical after changing net names in DE-HDL
}* u5 h; K y* {1 |% o3 N* M2043882 ALLEGRO_EDITOR SHAPE Shapes not updated to 'Minimum aperture for gap width' in Global Dynamic Shape Parameters window
+ f, W' e- ^ K8 ^) m" k( L" k2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update* o6 ?6 l( a) ?
2052063 ALLEGRO_EDITOR SHAPE Cannot import IPC2581 due to 'Shape intersects with itself'" I) N" s* E( B& I
2056478 ALLEGRO_EDITOR SHAPE Editing shape by sliding segment causes PCB Editor to fail due to 0-length segment in shape/ B, L( z* y' L M5 `: e: \4 @
2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present+ i( n% o( b8 i
2066473 ALLEGRO_EDITOR SHAPE Teardrops create strange copper shapes
. [: Y( c, C! R0 ^9 j8 t8 g2079698 ALLEGRO_EDITOR SHAPE IPC2581 import fails with error 'Shapes intersects with itself'2 e! m4 Q5 D0 I; n" r- i: j Y
2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in HotFix 048.
, C5 B' b( s7 D2 o' o2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash1 k4 Y* k9 q0 D8 k8 ?
2023755 ALLEGRO_EDITOR STEP Export STEP includes enclosure even when it is not selected.
( v$ h" p# g# U0 b& ?( {1881233 ALLEGRO_EDITOR UI_GENERAL Green/white canvas without grid when creating a board file (File - New)9 w$ q: |7 V* ]) o
1900525 ALLEGRO_EDITOR UI_GENERAL Resizing the update symbols UI causes the options to overlap and jumble up (refresh issue)5 [; t+ `& y, g9 K" ]" f
2003861 ALLEGRO_EDITOR UI_GENERAL Same y-coordinate returned for different vertical positions when creating board outline in HotFix 048
6 {0 g; N1 o4 J- J, v2033958 ALLEGRO_EDITOR UI_GENERAL Incorrect canvas display on creating a design from the Start page and then opening an existing design
, @0 A2 M& b+ y4 s- a! G3 V* p2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog is behind canvas9 a8 Z$ {8 `$ O) V- t4 d% h5 z2 K# F
2054429 ALLEGRO_EDITOR UI_GENERAL Editor stops responding until choosing Done after clicking Zoom by Point twice, q5 }- ]& g+ s$ @+ E) G
2059707 ALLEGRO_EDITOR UI_GENERAL 'HTTPS' links are not shown as hyperlinks when using allegro_html3 L8 P# f8 I% T+ s% ~1 D
2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden9 r. C: R1 r5 l! g+ c0 y1 O
2038105 APD DRC_CONSTRAIN APD crashes on update DRC in release 16.6* w. ~5 `( g; X. ^
2050674 APD PARTITION Cannot remove C-Point from a partitioned design
, o) ^2 z3 a% ^4 O2068814 APD WIREBOND Bond wires cross on auto-separate
7 a" M) T9 ]# e1967433 CAPTURE OTHER Cannot open DSN or OPJ files by double-clicking if Capture is already open. q. \- N8 N% T1 F' E% }8 g
1967332 CONCEPT_HDL COMP_BROWSER Crash in customer environment on clicking on last row border in PIM after filtering
5 O& M; v) v% a O* g2001759 CONCEPT_HDL COMP_BROWSER Using Modify Component crashes Design Entry HDL
4 Q% j8 u. | g& B7 t2020788 CONCEPT_HDL COMP_BROWSER Intermittent crash when clicking bottom edge of part selection table in the Modify Component window
8 n! A, _2 [8 e' U+ }3 X7 i2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved
, ]. O0 a- O5 F( l( L2 R: ~2013002 CONCEPT_HDL CORE Ability to regenerate Netgroup names to remove '_1' suffix
" W; m% ], Y _9 \6 E* k O2026637 CONCEPT_HDL CORE DE-HDL crashing often when launched from EDM Flow Manager- b3 z- Q3 H* g
2041145 CONCEPT_HDL CORE Set font size & color of netgroup names and netgroup taps
% G6 J% x% B/ t. q8 T# C/ z5 w' k2056743 CONCEPT_HDL CORE NetGroups appended with _1_1, some are empty, and inconsistent in DE-HDL CM and Allegro PCB Editor CM; L3 |9 X8 A! }" }/ g/ M0 c; |
2065889 CONCEPT_HDL CORE DE-HDL Modify command moves location of attached symbol properties
5 }7 H+ }" q, V0 A( P( `2074410 CONCEPT_HDL CORE Full net connectivity not shown in Allegro PCB Editor.! P- ~( q" t1 f+ G' I5 X9 D* c
2045717 CONCEPT_HDL RF_LAYOUT_DRI The RF PCB Options is greyed out when doing Import Physical on Linux with enterprise licenses: k1 W$ c' m b& u& R w
2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor1 e2 o0 y2 r; R+ p9 A
2050521 CONSTRAINT_MGR OTHER Unexpected Xnet removal from schematic when Export to PCB Layout is executed.
. {7 w, @; _2 z6 H4 r) `2066270 PCB_LIBRARIAN SYMBOL_EDITOR Unable to edit note text containing comma
" _' A4 _% l( S* a2069181 PCB_LIBRARIAN SYMBOL_EDITOR Pinlist window expand/collapse buttons act weird first time when invoked.
9 ]- h0 t1 d5 b1 P2070007 PCB_LIBRARIAN SYMBOL_EDITOR Project not found error in Symbol Editor when path contains space character$ q1 c k3 l" L. d& t- R
2072793 PCB_LIBRARIAN SYMBOL_EDITOR Right-click menu of formatting text objects is not consistent: second and third options are swapped
) {# x7 S* ]4 S2073138 PCB_LIBRARIAN SYMBOL_EDITOR New Symbol Editor: Do not allow duplicate properties
* @6 n; ?. S! C/ s6 J1957458 PSPICE FRONTENDPLUGI Refresh issue with Bias Display on a new design: bias value not updated
' ~, X; W- A" a7 P- N' D) v2022211 PSPICE FRONTENDPLUGI Bias Point results are not updated. ]! ?( R# |, R3 d* y' t7 g
2031058 PSPICE FRONTENDPLUGI PSpice bias values are not getting updated
' U$ v, R0 y' _2038021 PSPICE FRONTENDPLUGI Bias display is not updated8 c9 L3 z! R0 D- F
2055274 PSPICE FRONTENDPLUGI Capture crashes on SIMSETUP OK when two projects are open
9 g1 [; R2 R. @% h$ Z2053432 RF_PCB OTHER Property on RF component not transferred to new design not containing the component" F% l. p7 T4 A' n7 X- ]
2003341 SCM SCHGEN Unable to generate a schematic for hierarchical blocks3 H# r# O% M% E* y
2069924 SIP_LAYOUT DIE_ABSTRACT_ Conversion from co-design die to standard die / BGA / anything else must remove floating function pins.0 `4 E8 l+ r2 [& F# ]
2067894 SIP_LAYOUT OTHER sip database size is enormous for a small component definition used in fdesign
* p# B1 K2 t8 R2067987 SIP_LAYOUT OTHER Orphaned die attachment in SiP Layout cannot be removed
6 g/ J+ d3 e; q1 J% \4 q2 a' K2072857 SIP_LAYOUT OTHER SiP Layout crashes when using Find by Query and choosing 'Symbols'% d. R" r& t, A5 o4 v! U. z) f
2068973 SIP_LAYOUT REPORTS SiP Layout Missing Fillet report not catching a missing fillet in HotFix 051 and 052
5 O3 x) [' } d; O8 l- M2059533 SIP_LAYOUT SYMB_EDIT_APP SiP Layout: Cannot rotate bumps in Symbol Editor application mode
& M1 N5 U& e' l- u* x' ]1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error
, n: r/ I. Z; ?9 D7 q9 \2054869 SYSTEM_CAPTURE AUTOMATION syscapUtils.tcl command cnsAutoCreateDiffPair is broken due to missing acm_code.il and acm_config.txt files
4 e* Z- _ D% P- s1966488 SYSTEM_CAPTURE CANVAS_EDIT New folder rename box does not show the text typed.
5 p) i R/ ~+ e! I$ r1814813 SYSTEM_CAPTURE COMPONENT_BRO System Capture session log should specify the CDSSITE path for the current session
3 c& D2 m9 x" S8 C" w) `1977673 SYSTEM_CAPTURE COMPONENT_BRO adding reference blocks through add component error when cell name matches design name3 ?+ S7 j( y7 n
2027100 SYSTEM_CAPTURE COMPOSITE_FIL pstdedb.cdsz and netlist preview in System capture is not being updated when individual netlist files are written
) W2 i8 k$ H# O) i R, u% I1 n0 \1961274 SYSTEM_CAPTURE CONNECTIVITY_ Xnet removed during pin swapping9 V4 O& T1 A0 z2 i5 z" D
2041879 SYSTEM_CAPTURE CONNECTIVITY_ xnets on net with only pull-up resistor
7 W- n% n! ?) }; [9 k1889238 SYSTEM_CAPTURE COPY_PASTE Wire fails to connect during copy and paste! S3 U! j& e# E3 x8 m1 P
1993146 SYSTEM_CAPTURE DESIGN_EXPLOR Cannot move page up by only one position* e8 j* a- y$ X
1910941 SYSTEM_CAPTURE MISCELLANEOUS Parts that are not in any schematic page appear in netlsit and BOM3 ~/ u8 s+ J- ]* d
1902347 SYSTEM_CAPTURE PRINT Prints all sheets if one sheet is specified as the print range
5 j+ W9 R* p$ Q$ \. U& b2041272 SYSTEM_CAPTURE SMART_PDF Smart pdf displays component outline when component is not de-highlighted.+ ?& ?5 l% x* y" V& P1 \/ P
2065768 SYSTEM_CAPTURE SMART_PDF Custom Variable in Table Object not getting passed to PDF
2 K: A4 h/ H) c. A1 o1 K6 G1969243 SYSTEM_CAPTURE VARIANT_MANAG Export variant does not name file correctly if the filename contains a space
9 T$ X/ N' @. v( Q+ h: }# U x1990258 SYSTEM_CAPTURE VARIANT_MANAG Cannot paste copied preferred part to multiple parts with the same part number; t8 p6 m3 z( e6 p
1992250 SYSTEM_CAPTURE WORKSPACE Double-clicking a .CPM file runs System Capture but does not open project |
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