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Fixed CCRs: SPB 17.2 HF054
0 g- G7 G, J0 j" M04-26-2019' [+ \% P6 r% v3 h# g0 x! h
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, B7 U T' b' T- F2060269 ADW DBEDITOR Unable to create ECAD type mixed-case schematic model attributes% q X7 g7 b% @, o9 v2 o y# d. i& T
2030086 ADW LRM Cache part_table.ptf made by LRM Update cannot be read if it has null value in key property) `- T. L+ D5 Q1 p9 i
1975317 ADW PART_BROWSER Space at the end of line in CDS.LIB results in zero libraries being shown in new component browser
% n/ _3 g8 |2 z6 h2076340 ADW PART_BROWSER .helix folder needs to be deleted for PTF changes to take effect and to convert a design to cache
+ i" e" c, c9 ~$ @2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name
- e( w7 K. Q5 j; B# j8 `9 e2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design
! M- k& d) Y) b O- s4 \1 O. \8 v% I2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object
) E8 c1 C* N, c% G2054243 ALLEGRO_EDITOR 3D_CANVAS Plating is not shown on stacked vias in 3D canvas
3 x2 l7 L+ v! P P' u2 j- Q2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation
6 b* R6 P8 l/ ?. s3 j2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded/ Z: r Q; U8 i# e. `( x Z
2060489 ALLEGRO_EDITOR COLOR SKILL axlGlobalVisibility() issue in a partition file: VIA/SOLDERMASK_TOP subclass visibility not turned off
$ d5 a- B6 ?& ]9 ]2072695 ALLEGRO_EDITOR COLOR Clines of colored nets not colored when 'display_nohighlight_priority' is set
3 H. @+ i3 b; S/ b; [5 a3 N2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone) s3 y! \5 q- P$ N$ |1 \* D' X
2010812 ALLEGRO_EDITOR DATABASE PCB Editor STEP model offsets should follow origin movements
8 `9 @) J% d! O. l2 F, }+ D, K1 Q2011993 ALLEGRO_EDITOR DATABASE Change STEP model mapping when Symbol Origin is changed in DRA using Setup > Change Drawing Origin0 X8 r' t- o3 W- W# h; D- s7 J
2051596 ALLEGRO_EDITOR DATABASE Error for unsupported property in element
! _0 ?# ]2 I9 s+ o+ ` H- F3 r; x2056497 ALLEGRO_EDITOR DATABASE Place manual is slow: y! C! ]7 W& `/ V9 s. `
2059489 ALLEGRO_EDITOR DATABASE DBDOCTOR in batch mode with argument '-check_only' detects text error/ P4 A3 R5 C! a. O# s
2064268 ALLEGRO_EDITOR DATABASE PCB Editor crashes when running SKILL code
( l7 ^3 R2 g. A: C; M2068588 ALLEGRO_EDITOR DATABASE Crash on opening release 16.6 design in 17.2-20162 A. P/ T; x- O" x
2079131 ALLEGRO_EDITOR DATABASE axlChangeNet crashes PCB Editor in fast shape mode with Microsoft Visual C++ Runtime Library Error
3 t D& S5 N6 [4 |; U3 Q2034759 ALLEGRO_EDITOR DFM Importing DFT constraints on board does not assign csets to design but shows the csets- w! ?6 Q4 {$ Z9 H" C _8 m$ q' k5 q
2039992 ALLEGRO_EDITOR DFM Cset is not set in Pastemask element of DFA when importing XML Constraint File.
- h% u1 A9 W, A1 n1 g+ F2046824 ALLEGRO_EDITOR EXTRACT Extracta ECL_NETWORK View reports incorrect pin layer.
1 Q I( I, i c5 K9 @2048912 ALLEGRO_EDITOR IPC Running PCB Design Compare - Graphic mode reports ERROR (SPMHA1-273) 'Shape intersects with itself'" F+ l+ H W% ?% t% G) I7 s+ n( Q
2066597 ALLEGRO_EDITOR IPC Graphical compare not completed because of self-intersecting shape locations3 n! \: P7 l* V3 s/ i
2079719 ALLEGRO_EDITOR IPC IPC2581 import fails with error 'Failed to add (LW)POLYLINE'
" }( k( N& E/ y, }2066229 ALLEGRO_EDITOR NC Tool code missing in backdrill NC file on choosing 'Optimize Drill Head Travel' in NC Drill% ]; g" ~ t# Y4 T7 I' a
2070379 ALLEGRO_EDITOR NC After running backdrill some vias are shorted to other nets, F" A$ p V( S2 \5 J. D3 ]
2041881 ALLEGRO_EDITOR PAD_EDITOR Difference in locations of drill in pad editor and symbol editor* D9 k$ A, f; w7 W
2058852 ALLEGRO_EDITOR PAD_EDITOR Net associations lost on refreshing vias
( u+ W+ N i2 T8 ]) N6 c1 {2061580 ALLEGRO_EDITOR PAD_EDITOR Lock Layer Span settings specified in padstack editor not reflected in PCB Editor! \/ @" f1 Q5 w5 K( y% U
2048116 ALLEGRO_EDITOR REPORTS Extracta command files not visible in Tools-->Reports when there is a space present in the textpath variable
, G4 l) T& C/ W( R0 f, t. i0 ~2038949 ALLEGRO_EDITOR SCHEM_FTB Netrev is slow if there is an input board file with many modified components
" [4 D4 [4 n. T6 t2 [% W7 x, V2052758 ALLEGRO_EDITOR SCHEM_FTB Connectivity objects are being reported as Added and Deleted in Constraint Differences Report& n6 z( a! D B) V4 X
2066099 ALLEGRO_EDITOR SCHEM_FTB Inconsistent net names on export physical after changing net names in DE-HDL5 E4 q0 p: x& H" i
2043882 ALLEGRO_EDITOR SHAPE Shapes not updated to 'Minimum aperture for gap width' in Global Dynamic Shape Parameters window
* ^$ o K9 G& w. |2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update
' E0 Q1 ?/ e+ _2 v$ W2052063 ALLEGRO_EDITOR SHAPE Cannot import IPC2581 due to 'Shape intersects with itself'9 e" z) D: Z9 r8 Q$ G0 Z$ N
2056478 ALLEGRO_EDITOR SHAPE Editing shape by sliding segment causes PCB Editor to fail due to 0-length segment in shape
: j+ w, _. E o" N8 L- t% F2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present
& z7 t4 E7 B4 |- A9 ]6 `# W1 V2066473 ALLEGRO_EDITOR SHAPE Teardrops create strange copper shapes/ g5 J# N* W2 n2 |; c& g ^
2079698 ALLEGRO_EDITOR SHAPE IPC2581 import fails with error 'Shapes intersects with itself'! z/ d, O! C8 K/ u
2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in HotFix 048.
& `8 I" n, @2 V! M/ z2 P: a, @2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash
5 G, {1 y/ f# X. ]2 `2 `- r' B2023755 ALLEGRO_EDITOR STEP Export STEP includes enclosure even when it is not selected.
5 K$ D0 k# s. u' K1881233 ALLEGRO_EDITOR UI_GENERAL Green/white canvas without grid when creating a board file (File - New)
& X: N9 a' @7 s9 \. ^ K1900525 ALLEGRO_EDITOR UI_GENERAL Resizing the update symbols UI causes the options to overlap and jumble up (refresh issue)
% V. N \7 Q. M' D0 c2003861 ALLEGRO_EDITOR UI_GENERAL Same y-coordinate returned for different vertical positions when creating board outline in HotFix 0488 t' I4 r0 w( I1 C( n R/ z! S
2033958 ALLEGRO_EDITOR UI_GENERAL Incorrect canvas display on creating a design from the Start page and then opening an existing design+ B3 ?; n/ B; g, m9 R
2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog is behind canvas+ J9 G1 z8 s; x9 ]# X
2054429 ALLEGRO_EDITOR UI_GENERAL Editor stops responding until choosing Done after clicking Zoom by Point twice
! [9 b6 x" B& ]) {+ R" p2059707 ALLEGRO_EDITOR UI_GENERAL 'HTTPS' links are not shown as hyperlinks when using allegro_html
& _) \: W. Y9 y$ O, H: L/ N2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden. n/ T1 B% ~; S- a
2038105 APD DRC_CONSTRAIN APD crashes on update DRC in release 16.61 x/ V8 j' D* t' Q2 p
2050674 APD PARTITION Cannot remove C-Point from a partitioned design6 J% N1 i7 S. O) a: }8 I
2068814 APD WIREBOND Bond wires cross on auto-separate6 l$ N4 p- d B3 f% T ^
1967433 CAPTURE OTHER Cannot open DSN or OPJ files by double-clicking if Capture is already open
; N% |" C: z( H2 ~+ J6 e2 k1967332 CONCEPT_HDL COMP_BROWSER Crash in customer environment on clicking on last row border in PIM after filtering
: f% N/ r* G( t6 N& ~3 P2001759 CONCEPT_HDL COMP_BROWSER Using Modify Component crashes Design Entry HDL6 c/ i: |- `6 u9 ~* K1 p/ s
2020788 CONCEPT_HDL COMP_BROWSER Intermittent crash when clicking bottom edge of part selection table in the Modify Component window
# Y ^4 t2 ~& @+ Y% O! o1 Z7 Y2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved. D8 c! q/ z. m0 J" T% l j
2013002 CONCEPT_HDL CORE Ability to regenerate Netgroup names to remove '_1' suffix% w+ \# g5 n7 t- R9 ~
2026637 CONCEPT_HDL CORE DE-HDL crashing often when launched from EDM Flow Manager
- ~$ G0 Y8 n& @) g2041145 CONCEPT_HDL CORE Set font size & color of netgroup names and netgroup taps
* A8 X! R. V; `2056743 CONCEPT_HDL CORE NetGroups appended with _1_1, some are empty, and inconsistent in DE-HDL CM and Allegro PCB Editor CM; {3 G. {4 @3 e
2065889 CONCEPT_HDL CORE DE-HDL Modify command moves location of attached symbol properties
+ D( A- c! h0 N6 ~. I; ?, @$ ~2074410 CONCEPT_HDL CORE Full net connectivity not shown in Allegro PCB Editor.! {0 y0 _9 S- Q6 l7 }* \! O* k: n! t' m
2045717 CONCEPT_HDL RF_LAYOUT_DRI The RF PCB Options is greyed out when doing Import Physical on Linux with enterprise licenses
" @2 k- |& x4 K' ?! |: V- H2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor
H5 u5 f: E1 v* p6 v- E A2050521 CONSTRAINT_MGR OTHER Unexpected Xnet removal from schematic when Export to PCB Layout is executed.! t0 \# S: F' k
2066270 PCB_LIBRARIAN SYMBOL_EDITOR Unable to edit note text containing comma
/ Q% X# H0 M# ~2 G; T. Z9 ?, i2 U2069181 PCB_LIBRARIAN SYMBOL_EDITOR Pinlist window expand/collapse buttons act weird first time when invoked.
- c/ i) j, k- ]" Q# F: z2070007 PCB_LIBRARIAN SYMBOL_EDITOR Project not found error in Symbol Editor when path contains space character/ ]* o6 }" D( N; n' t
2072793 PCB_LIBRARIAN SYMBOL_EDITOR Right-click menu of formatting text objects is not consistent: second and third options are swapped
$ Z( R9 A3 f% t- V6 p; f0 H2073138 PCB_LIBRARIAN SYMBOL_EDITOR New Symbol Editor: Do not allow duplicate properties
1 u; V7 K& W3 S! N8 v+ m1957458 PSPICE FRONTENDPLUGI Refresh issue with Bias Display on a new design: bias value not updated
{8 o/ {$ J+ u3 R2022211 PSPICE FRONTENDPLUGI Bias Point results are not updated6 k2 X3 K4 ]% P: R( a
2031058 PSPICE FRONTENDPLUGI PSpice bias values are not getting updated
4 b# T7 w4 L3 g; l& B8 q2038021 PSPICE FRONTENDPLUGI Bias display is not updated
1 G/ b' ]0 p+ [2 V8 u2055274 PSPICE FRONTENDPLUGI Capture crashes on SIMSETUP OK when two projects are open1 n# D: N$ |* r3 Y& W1 i1 L( Q
2053432 RF_PCB OTHER Property on RF component not transferred to new design not containing the component' Q0 u- K% Y# I# L2 X
2003341 SCM SCHGEN Unable to generate a schematic for hierarchical blocks7 I; h" s; p I
2069924 SIP_LAYOUT DIE_ABSTRACT_ Conversion from co-design die to standard die / BGA / anything else must remove floating function pins.
7 ?: Z# I2 ?3 {: ?2 F- s9 S+ k# V' b2067894 SIP_LAYOUT OTHER sip database size is enormous for a small component definition used in fdesign
/ s, G% q5 N# H2067987 SIP_LAYOUT OTHER Orphaned die attachment in SiP Layout cannot be removed
5 e9 m2 P) _' L/ G' s1 m2072857 SIP_LAYOUT OTHER SiP Layout crashes when using Find by Query and choosing 'Symbols'
. H4 i+ d+ i) }7 j2068973 SIP_LAYOUT REPORTS SiP Layout Missing Fillet report not catching a missing fillet in HotFix 051 and 052
; Z# l/ Y: {# }$ O( A2059533 SIP_LAYOUT SYMB_EDIT_APP SiP Layout: Cannot rotate bumps in Symbol Editor application mode
; Q; E6 w7 Z+ S o. A4 ?( Q7 T1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error* l+ n, L5 e5 s5 ~
2054869 SYSTEM_CAPTURE AUTOMATION syscapUtils.tcl command cnsAutoCreateDiffPair is broken due to missing acm_code.il and acm_config.txt files
+ H d0 P/ l1 L( U8 }1 `1966488 SYSTEM_CAPTURE CANVAS_EDIT New folder rename box does not show the text typed.
% y* G4 e: R# V8 A- G1814813 SYSTEM_CAPTURE COMPONENT_BRO System Capture session log should specify the CDSSITE path for the current session
/ T9 L: v9 R' I E! w- n% n3 J8 H1977673 SYSTEM_CAPTURE COMPONENT_BRO adding reference blocks through add component error when cell name matches design name
& v0 V$ u7 f* y P) t, y6 R$ Q2027100 SYSTEM_CAPTURE COMPOSITE_FIL pstdedb.cdsz and netlist preview in System capture is not being updated when individual netlist files are written
6 U9 Z% L/ P3 K" _ k% @. S, H) l1961274 SYSTEM_CAPTURE CONNECTIVITY_ Xnet removed during pin swapping0 T# v& a6 C% P, |
2041879 SYSTEM_CAPTURE CONNECTIVITY_ xnets on net with only pull-up resistor5 I. H2 k: J- R6 m7 t$ G# x
1889238 SYSTEM_CAPTURE COPY_PASTE Wire fails to connect during copy and paste" f( S r; R# k* L
1993146 SYSTEM_CAPTURE DESIGN_EXPLOR Cannot move page up by only one position
1 m: y- M& H4 x+ W$ o1910941 SYSTEM_CAPTURE MISCELLANEOUS Parts that are not in any schematic page appear in netlsit and BOM
6 ^% Q: ], U8 v! }8 I1902347 SYSTEM_CAPTURE PRINT Prints all sheets if one sheet is specified as the print range8 Z& M* c" ^1 B- p' t
2041272 SYSTEM_CAPTURE SMART_PDF Smart pdf displays component outline when component is not de-highlighted.
9 T: W" ~: ^- p% j2065768 SYSTEM_CAPTURE SMART_PDF Custom Variable in Table Object not getting passed to PDF
8 `0 E' _9 \4 a+ v7 z. o& \1969243 SYSTEM_CAPTURE VARIANT_MANAG Export variant does not name file correctly if the filename contains a space
1 s* k& h, l/ s {1990258 SYSTEM_CAPTURE VARIANT_MANAG Cannot paste copied preferred part to multiple parts with the same part number5 k* Z( n+ R+ a' N) j- l8 v* J4 p
1992250 SYSTEM_CAPTURE WORKSPACE Double-clicking a .CPM file runs System Capture but does not open project |
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