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LBSALE[10]LBSALEMIXED-SIGNAL AND DSP DESIGN TECHNIQUES
% v. E5 b+ K( K+ Q' E5 A8 w& {9 tSECTION 1; @ X$ q" L/ q' ^
INTRODUCTION2 m( n; n# b$ y( D6 _
SECTION 20 U0 D! N& \% o7 ~7 \* i
SAMPLED DATA SYSTEMS
' I' c ]2 I3 S0 U9 K0 w Discrete Time Sampling of Analog Signals5 @6 {+ A5 o. Q# s9 Z5 u5 P
ADC and DAC Static Transfer Functions and DC Errors
4 z. u' W$ i( Y, _" k AC Errors in Data Converters7 x& u9 q. G& _/ T o
DAC Dynamic PeRFormance& ?2 }- t9 j. f& j. ^- G
SECTION 3/ h& P; b$ P! g3 J' q" {# ?
ADCs FOR DSP APPLICATIONS
: e( V9 P1 T$ k" l" N! ]) ?5 R- x Successive Approximation ADCs8 c0 n! h2 L9 Y! f' j( E$ G! a
Sigma-Delta ADCs0 H7 P0 C: k% g
Flash Converters$ R) v& S3 m g/ F
Subranging (Pipelined) ADCs# ?( _% T* h$ N) F( y. l
Bit-Per-Stage (Serial, or Ripple) ADCs; _" V8 w9 i) q' o* B
SECTION 4
/ j& C8 Q. [ A/ C2 ZDACs FOR DSP APPLICATIONS
4 V; Y- _# W) N8 m8 ` DAC Structures
4 a" v+ b! T! `! [2 P V Low Distortion DAC Architectures+ Z; o* d% H6 R/ T. V+ g
DAC Logic$ \) u6 u+ E. x: |! }
Sigma-Delta DACs# s5 R, @: A& b) c
Direct Digital Synthesis (DDS)
0 n$ V, j' G8 c0 [) MSECTION 5
- `& r4 v) B- r5 i" dFAST FOURIER TRANSFORMS
/ ?* X3 \4 T- X% W# \ The Discrete Fourier Transform
) N. Y5 _' ~& S6 q' v" g$ w The Fast Fourier Transform6 e$ D. S" l0 S9 n1 `7 l# S
FFT Hardware Implementation and Benchmarks9 S* X9 c. v. _4 _& x! Z6 g
DSP Requirements for Real Time FFT Applications
& O! |: O) \2 V( J: w8 | Spectral Leakage and Windowing
9 g- e) ~, n* ]7 USECTION 6
8 C6 P8 O) E5 B2 f9 G( S! X$ ADIGITAL FILTERS
. L4 q# E3 P' v, L* w* v& D* I2 L Finite Impulse Response (FIR) Filters
7 ~( f4 y& e9 h3 G8 B Infinite Impulse Response (IIR) Filters
4 l9 Z% q7 E4 R e# _ Multirate Filters
. H" X. u& Y% P- ~9 ~ Adaptive Filters
0 b; K7 M8 L+ q: t$ ZSECTION 7
: M( w' Q. f, M* i- o' BDSP HARDWARE- G7 J2 b! l+ W* f2 D* u% y l) j8 T' ]
Microcontrollers, Microprocessors, and Digital Signal& r+ z8 k- b% ^+ F
Processors (DSPs)
! p! A. m' e! k% { N8 ] DSP Requirements+ w7 E3 P" B, ~9 |+ K' V
ADSP-21xx 16-Bit Fixed-Point DSP Core
0 k3 d1 w% r& n; N5 s) V Fixed-Point Versus Floating Point
! S( q- |! j! k( |0 [# f ADI SHARC® Floating Point DSPs$ L2 E, L6 x7 d! x+ {8 Z1 R
ADSP-2116x Single-Instruction, Multiple Data (SIMD)# R. E. C" M% Q2 R
Core Architecture# P2 G0 X% b6 N( L1 a
TigerSHARC™: The ADSP-TS001 Static Superscalar* F2 b- [7 ~7 I
DSP, D* f+ b* }8 v9 K- E" F" a. [& N
DSP Benchmarks
' w+ s2 t) x' L2 K7 x DSP Evaluation and Development Tools, }% W% K. ?1 B1 S" b8 k
SECTION 8! l3 v b& `0 v* D4 ~& f( v. p
INTERFACING TO DSPs8 |/ T3 ] u" [5 k9 i2 ~
Parallel Interfacing to DSP Processors: Reading Data
' a$ e$ q5 C# |& @& E, sFrom Memory-Mapped Peripheral ADCs
6 c( C1 c: ]* m$ I ^& N- E2 I Parallel Interfacing to DSP Processors: Writing Data to
) M* K4 f: i1 kMemory-Mapped DACs5 o' v+ d$ |$ ^+ y+ U: r8 a( p
Serial Interfacing to DSP Processors
$ }, R, A5 E! o2 ]: g Interfacing I/O Ports, Analog Front Ends, and Codecs to+ _; x, L7 H0 g' o8 E
DSPs2 G% c' {3 D' a8 I I l
DSP System Interface% S/ X! e/ M0 h4 q, \
SECTION 9
, ]0 W) Q2 S( q% X# u6 ODSP APPLICATIONS
$ s8 J) l! F% l* ]& S3 N" U% P High Performance Modems for Plain Old Telephone. m3 _' m2 L( ^/ }3 M; B U
Service (POTS)
! ~6 R# G8 V# a% [. W Remote Access Server (RAS) Modems
7 A% F8 X2 y0 A6 i1 n; j5 Q9 w ADSL (Assymetric Digital Subscriber Line)
: B' Q: k! F/ T: G* e& }6 o ?) [- ` Digital Cellular Telephones
$ G/ T2 W$ J) [/ J1 |' | GSM Handset Using SoftFone™ Baseband Processor
! I, N, W( c/ H& n6 |0 x# fand Othello™ Radio g( Z7 f/ f1 @4 ?
Analog Cellular Basestations
/ }7 p. k. Z4 m2 J' Y4 a Digital Cellular Basestations+ [ c* {, x9 x8 j
Motor Control$ C/ {, g! X, J' z, I( Y
Codecs and DSPs in Voiceband and Audio Applications( Y. i6 K1 r* F' p# R, T
A Sigma-Delta ADC with Programmable Digital Filter/ p% j. k3 V' | W
SECTION 10
. ?/ `" Z$ H3 A$ X, PHARDWARE DESIGN TECHNIQUES& G) ], h, p; i! C1 b- @
Low Voltage Interfaces
* E; u7 V4 g/ U Grounding in Mixed Signal Systems4 H5 |. S* S! o8 O. h2 h
Digital Isolation Techniques
! l% X( }3 v" q Power Supply Noise Reduction and Filtering
) {' o# Q+ M2 j: c Dealing with High Speed Logic
2 _+ H s) @" g- n# d% X; Y' g- |INDEX文字 |
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