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Since the earliest days of microprocessors, system designers have been plagued by a problem in which the! i, [! w! {- ]! x- H% g
speed of the CPU's operation exceeded the bandwidth of the memory subsystem to which it was connected.
3 x0 F( T! h ~& M- O9 sTo avoid wasting CPU cycles while waiting for the memory to fetch the requested data, the universally2 ~, W$ E7 u' S
adopted solution was to use an area of faster (and thus more expensive) memory to cache main memory data.
# a$ h4 f1 K, ~& T) qThis solution allowed the CPU to operate at its natural speed as long as the data it required was available in
$ ?( `0 ?9 Y! Z1 y0 n' f, a# _the cache. |
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