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DATE: 05-28-2016 HOTFIX VERSION: 071
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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. i/ S4 _, r, M7 k( H1452838 concept_HDL CORE Apparent discrepancy between Bus names and other nets$ [) n0 I2 R, H" y* n7 u4 c' g
1469146 ADW LRM ERROR(SPCODD-5): Pin '1<1>' on the following primitive instance cannot be packaged in package
: {/ U7 ?; \3 A: W1499515 ADW COMPONENT_BROWSE The Search Criteria property value is automatically being set in the ADW Component Browser
9 C+ Y3 T7 T. y9 f/ z# F. Y- Z1524947 SIG_INTEGRITY SIGNOISE SI Base, PCB SI: Custom Stimulus is not recognized correctly; R: M! l, A! g7 v3 e/ j
1532162 CONCEPT_HDL CORE The Rename Signal command does not update split symbols.% m+ j! m7 t8 H2 k9 m
1543997 CONSTRAINT_MGR OTHER Import Logic is overwriting the constraints in attached design.
" e7 r0 A6 S7 H9 g1544675 allegro_EDITOR OTHER Export libraries corrupts symbols if paths do not include the current directory (.)
( Q8 A% x4 O* e0 }2 L- \( `0 @1549097 CONSTRAINT_MGR XNET_DIFFPAIR Need to warn users creating differential pair(s) in the Physical Tab with nets that have voltage properties set2 G) D+ g% |9 [: O" z
1551934 ALLEGRO_EDITOR skill axlBackDrill command is not analyzing new layer set when application mode is set to 'None'
- H: k; o/ q6 d; o! t1554919 ADW LRM LRM does not find PTF data for cell 'res' in the reference library
4 W( Y7 T* O6 u1555009 CONCEPT_HDL INTERFACE_DESIGN Not possible to rename NG) n1 {0 g' C% v& I4 i, J( n- A
1557542 ALLEGRO_EDITOR OTHER DXF export creates strange result for donut-shaped polygon( ]6 ^& G; Q1 v: Q- d
1559136 ALLEGRO_EDITOR EDIT_ETCH Cannot connect floating clines to vias with nets# V. E7 O+ H+ |& w2 r& T9 ~& W
1560301 CONCEPT_HDL CORE DE-HDL hangs when Edit menu commands are called on Linux if xclip is open
. N+ b* P7 f1 M! O2 i% t3 Y" ?1560804 ALLEGRO_EDITOR OTHER Film records order gets reversed when using File - Import - Parameters after File - Export - Parameters L1 n" c8 B, m
1564036 CONCEPT_HDL CORE User-defined custom variables are not getting populated in the TOC6 o2 U2 S0 W6 K6 }" z& @ T/ v
1564545 CONCEPT_HDL OTHER Signal model property deleted from an instance is not deleted from the instance pins
) ]/ N; |9 F' r7 D1564552 CONCEPT_HDL CORE Find Net should zoom to the nets on schematic canvas. k T- g& }, C2 l! o1 F
1566119 CONCEPT_HDL CORE Right-clicking the schematic to add a component does not show all the schematic symbol versions+ e/ p* _1 y6 R- t7 ~$ m2 W
1566848 ALLEGRO_EDITOR ARTWORK Board Outline artwork is incomplete
' h) n- z" H& D7 C0 q3 g1567290 ALLEGRO_EDITOR MANUFACT Import Artwork fails to import a shape.
. h9 ]+ f3 n4 @' O1567587 ALLEGRO_EDITOR MANUFACT Extended tool name in header of drill file is not correct
6 ]' u* K0 p* g) C( m# f1569056 CONCEPT_HDL CORE Opening New Cascaded Window Causes Graphics Artifacts on Old Window( A) ~* E W5 n8 o" q
1569087 ALLEGRO_EDITOR DRC_CONSTR Running DRC Update gives the message 'Figure outside of drawing extents. Cannot continue.': ]4 \4 _6 Z3 n9 Q9 U
1569147 CONCEPT_HDL CORE Signal Name AutoComplete Drop Down List Not Correctly Displayed
6 ]+ o$ O3 h9 u6 c& H1569924 CONCEPT_HDL CHECKPLUS ERROR (body_to_physical_check) - Pin name(s) not found in package : PEX_REFCLK0_N* PEX_REFCLK1_N*...% o$ k& w# H7 W9 w: D- ]( j
1570419 CONSTRAINT_MGR CONCEPT_HDL How do I add a customized worksheet custom property weblink in Constraint Manager
* p0 |3 w, T/ W# j' L8 _) W1570624 APD ARTWORK Artwork file has missing voids on a layer and is causing a short
& O/ G# c/ q) [( j* e2 P1570678 F2B DESIGNVARI Variant Editor error when adding an RSTATE property& D7 k* D* @# K+ S% K
1571113 CONSTRAINT_MGR DATABASE Reports generated from cmDiffUtility show the differences in mm units only C: Z9 h* i/ S3 j* o* P2 ?5 P# U
1572593 ALLEGRO_EDITOR ARTWORK ARTWORK: 'Draw holes only' option does not match display
/ g% O2 e/ s; s& d4 V/ ^# }1573205 CONCEPT_HDL CORE dsreportgen is unable to resolve the physical net names (PHYSNET)5 n4 ^8 Z' X+ \2 ~
1573970 CONCEPT_HDL ARCHIVER archcore fails to archive the <project CPM>.arch file. J' |4 H1 P4 p/ b2 E
1574381 CONCEPT_HDL OTHER Packager crashes with some advanced settings0 X N# K, s Y: n* d2 t7 W1 Y
1576100 ALLEGRO_EDITOR SYMBOL Update symbol crashes, creates '.sav' file, but shows update was successful in 'refresh.log'- o" u \( ^" W9 W% Z4 G
1580103 ALLEGRO_EDITOR DATABASE dbstat of 16.6 does not recognize 17.X files
" N3 ?6 d' T5 v( P$ E# @ t3 `/ U5 y' o1 T
DATE: 04-22-2016 HOTFIX VERSION: 0699 L+ @: p4 z6 ~, j
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===================================================================================================================================
, @* X: R) J: d) I1272355 F2B DESIGNVARI Property changes on replaced component shows incorrect result in BOM output: E! n5 {) U" n! r$ O! }; T
1483136 ADW COMPONENT_BROWSE About searching the parenthesis or comma in Component Browser of ADW Mode
9 k/ M- f9 i. Z# J5 S1488909 ALLEGRO_EDITOR DRC_CONSTR Test Via causes net scheduling verification to fail
1 S+ I8 x' H% i: a% O1498389 SIP_LAYOUT DIE_GENERATOR Provide the ability in the 'die in' command to specify flip chip as a DIE symbol- B. k+ l: w# ?! e( L5 B
1506672 ALLEGRO_EDITOR INTERACTIV Replicate Place - Shapes are missing
S6 \% s5 L; u* _& I% E# x! F1523532 F2B PACKAGERXL Adding subdesign names in the "Use subdesign” or “Force subdesign" sections hangs for more than a minute
) d3 k: _( t0 O c- ^ w5 f1525783 CONCEPT_HDL CORE \BASE scope does not work for SYNONYMed global signals
$ ?, Y- i+ g( g; e) u1529846 ALLEGRO_EDITOR SHAPE Some shapes are not generated in the artwork2 ~) G6 b4 h3 c% D# s
1537499 CONCEPT_HDL CORE Adding the same version (already placed) with the same split block name should not be allowed
$ V9 n* J2 X% I- w( k0 T. R1542334 CONCEPT_HDL CREFER creferhdl leaving lock files in sch_1 folder; H( R1 I0 ?; ` E s2 w/ e9 K- A
1543410 ADW LRM LRM shows confusing pat status. It reports that update is needed but clicking update doesn't work) r2 |1 Q: g) A( c \
1546141 ALLEGRO_EDITOR SHAPE Shapes missing from Artwork
# p2 t; W7 H; h, ?/ a p1546877 CONCEPT_HDL CORE Align Left on Wires Fails With Incorrect Error Message
' ^! g) q/ N$ j$ S1548953 CONCEPT_HDL CORE Genview generates a symbol with strange graphics - lines going to a single point# l6 k( g ^4 W9 Z+ ^6 d' t( J' T3 j3 d
1548978 ALLEGRO_EDITOR MANUFACT Shape not voiding clines: S' H) w9 {( C2 }( `+ [
1550941 PCB_LIBRARIAN PTF_EDITOR PDV Part Table Editor new column sorting causing problems6 @( f8 x9 k r, R- P
1553950 ALLEGRO_EDITOR SKILL Executing axlUIControl('pixel2UserUnits) crashes Allegro
5 g2 K5 R- e: P: `, I1554333 CONCEPT_HDL CORE Changed connectivity error when aligning ports attached to netgroups& ~( U3 x' v/ b3 G" L! F
1555092 SIP_LAYOUT DEGASSING Degass offset is not working with hexagons4 M) S: O) p y# q0 I
1556261 ALLEGRO_EDITOR DATABASE Running DBDoctor on board file gives an error"Illegal database pointer encountered, Exiting DBDOCTOR." and crashes
/ e3 Q! b7 y8 ]% X4 K" B1557716 APD OTHER Stream out fails with request to terminate detected - Program aborted
) O) G% c% F7 j1559951 SIP_LAYOUT SYMB_EDIT_APPMOD Wrong bump locations after Symbol Editor -> Refresh co-design die) V0 N# F: P: M3 r. K# l
1560197 CONCEPT_HDL CORE bomhdl adds extra charcters to subdesign_suffix when generating hierarchical BOM( _& }/ T2 \' V0 B% W* i
1562537 ALLEGRO_EDITOR mentor Mentor BS to Allegro 16.6 results in Fatal Error
% W4 {6 s+ C, z1564203 ALLEGRO_EDITOR ARTWORK ARTWORK : Can't generate negative film., }6 t1 U. r# J. ]1 ?1 C! `
7 G1 a% R. M$ m5 Y3 W% S; h7 L
DATE: 03-23-2016 HOTFIX VERSION: 068( n6 k! J/ k. ~8 c. W( @6 V" v t" A" f
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===================================================================================================================================
7 f0 X1 A& t4 t1522411 FLOWS PROJMGR License selection should persist on invoking Layout from Project Manager$ ]5 {' Q# _9 K, b' ~% }" Z6 `6 W3 ]: c& M
1544614 ALLEGRO_EDITOR SKILL Associative dimension data reaches the 'psm' file despite deleting the layer on which it was set in the 'dra' file
9 K3 H3 Q" i$ \. T1545909 ALLEGRO_EDITOR UI_FORMS Show 'microvia' checkbox in 'Blind/Buried Vias' form only with the 'Allegro_PCB_Mini' license ^& t9 H. `9 ~4 p- t1 x4 I
1546842 ALLEGRO_EDITOR OTHER Unsupported characters: Not being reported by 'netrev' and causing nets to short9 T. T9 t2 k4 H$ Z T
1547224 CONCEPT_HDL CORE Lock the 'PATH' property once it is assigned by system
% K! O* Z' Q9 b$ j2 d# k1547584 SIP_LAYOUT OTHER SiP - Design Variant - delete embedded layer if not selected.
8 W9 A! v. t, ~* V5 A4 P" G8 ]. \1548116 CONCEPT_HDL CORE Some versions of Technology Independent Library do not appear when adding a symbol( V P# u4 I1 u% O: u: {. s" e- J% x
1548151 ALLEGRO_EDITOR INTERFACES Exporting a step file gives a component rotation mismatch in the *.stp file
" M% a+ R) T: z6 z! r1548421 F2B BOM Parts with same 'BOM_IGNORE' set do not behave the same way in the BOM report7 |( L( C, J) D' Y0 b% T7 I8 m; g; A( i
1549105 APD OTHER 'Stream out' fails with message: 'Request to terminate detected. Program aborted'
. \" B# G8 F# ^ m% B1549662 ALLEGRO_EDITOR OTHER Import parameters fails if your parampath does not have ./ v! J6 X+ L/ k4 p
1549836 CONCEPT_HDL CORE Tools -> Customize -> Keys -> Reset does not actually reset keyboard shortcuts" {% ^$ D" R# b0 g
1550052 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes when copying symbols5 V; v. c9 x8 e0 c$ d2 @
$ P1 @7 i% M$ s5 a8 j7 e/ ~DATE: 03-11-2016 HOTFIX VERSION: 067
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1482953 ALLEGRO_EDITOR DATABASE Part change disassociates parts from Group. l6 x/ l2 Q5 b$ h4 P
1484075 ALLEGRO_EDITOR pads_IN 'pads_in' imports ASSEMBLY_TOP and PLACE_BOUND_TOP outlines that are defined as shapes as lines
0 v6 O& C5 Q% m/ P& ^ N1519155 ALLEGRO_EDITOR OTHER IPC-2581-B Negative Plane Error
5 L! U& b, \% D S' v1528075 CONCEPT_HDL OTHER Auto Generate: DML model assignment fails with error 'There is PHYS_DES_PREFIX property in PTF file.'
6 Y: n* G: \4 N1528398 ALLEGRO_EDITOR SCHEM_FTB Problem with pin number format used in NC property; k, c. a: X2 P0 p- Y
1529178 SIG_EXPLORER OTHER Values not transferred correctly for PinPairs when created ECSET from a net' y2 g: @. u5 A9 W: x
1529720 CONCEPT_HDL COPY_PROJECT Running ADW copy project does not update the 'master.tag' file
}; X6 }! g" R D% [! F- `1530707 CONCEPT_HDL CORE Request to recover a 16.6 design after DE-HDL crashes7 ? U! f, ]" Y% k: z3 q; k3 t
1532124 CONSTRAINT_MGR SCM 'File - Export - Technology file' in Constraint Manager crashes SCM if .tcf file is missing
& X0 @& w6 q7 p1532788 CONSTRAINT_MGR OTHER Pin pair is hidden when Highlight Filter is ON in Constraint Manager" q5 Y! `" Y2 v! z3 ^% ^& [
1536912 CONCEPT_HDL CORE Customizing keys in DE-HDL - Disallow mapping a command to alphanumeric characters: F# v9 V* i: f8 ?1 `! i5 o& }
1537055 CONCEPT_HDL CHECKPLUS Rules Checker - POWER_PINS value not obtained when schematic instance has the POWER_PINS and POWER_GROUP properties
) R2 J' D( l" F1537278 SIG_EXPLORER SIMULATION SigXplorer (Allegro Sigrity SI) crashes when simulation is viewed in SystemSI Waveform Viewer7 n1 A0 K/ j/ s, k
1537339 CONCEPT_HDL INTERFACE_DESIGN No warning is flagged when moving a Net Group over a net) } a0 f& l4 k7 N
1537521 FLOWS PROJMGR Do not allow project creation if there are spaces in directory or file names on the Linux platform
, D) X& I8 z2 V& N1 t1539227 CONCEPT_HDL CORE Renaming a page from the hierarchy browser crashes the schematic editor.6 I- G6 w" @2 ^( s8 M3 l
1541532 SCM SCHGEN Generate Schematics crashes with 'Out of Memory' error
$ Y$ W! D4 [5 T" S1541589 ALLEGRO_EDITOR INTERFACES STEP model incorrectly shown in 3D viewer. Shows pins as angled.
" W2 P, ^" q! d4 \7 ~1541680 CONCEPT_HDL DOC A dot (.) or period in design name created 2 separate design folders in worklib
# k! C7 {$ Z9 e: i6 v1541687 ALLEGRO_EDITOR PADS_IN PADS closed polygons are imported as lines
r% p% a1 K* t7 l8 `+ J( D1542722 ALLEGRO_EDITOR INTERFACES IDX export: RefDes and PART_NUMBER missing for mechanical symbols
' c) n/ N# [1 d. l4 m+ D- t* r! D( _1542817 ALLEGRO_EDITOR DATABASE Import Netlist not getting completed on specific board7 B1 \- e2 U' Q3 Z' T8 d
1544060 SCM SCHGEN Generate Schematics causes Allegro System Architect to crash
; b! ]4 y0 u; j/ b9 K: {1544633 APD STREAM_IF The 'stream out' command causes Allegro Package Designer to crash
" X& E: |. B' ]2 S1544698 ALLEGRO_EDITOR PLACEMENT 'place replicate' does not add clines and vias to fanouts if fanouts are marked
) \, |# y8 d# q, V+ a$ {' w1544859 APD PARTITION Timing vision menu is missing in APD/SIP partitions.
0 K' ~+ v; x. U( s! V1545136 ALLEGRO_EDITOR PLACEMENT All fanouts are marked as part of one symbol instead of the symbols they attached with
/ B8 p- S' ?. L1545370 APD OTHER Pads in .mdd file getting placed on different layers as compared to the design
! {$ H; Z9 u c. Y7 W, h7 R
# E, ?' C$ H7 q. }# fDATE: 02-26-2016 HOTFIX VERSION: 066
0 \ v/ C" _* {" A o===================================================================================================================================
2 k! F7 O( H+ Q4 uCCRID PRODUCT PRODUCTLEVEL2 TITLE
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1523426 ALLEGRO_EDITOR DRC_CONSTR Dynamic shape not adjusted based on keepout; DRC generated( ~3 H: M" \0 O& x" y& F
1526729 SPIF OTHER Exporting a dsn file causes PCB Editor to crash - in the interactive and batch modes0 }$ x' T7 n) d) R$ S* f
1529209 CONCEPT_HDL CORE When adding a component symbol version, the More option does not show all the versions
& E; [- W; ^8 a$ O1530888 ALLEGRO_EDITOR INTERFACES IPC2581 does not generate production files and fails with a segmentation fault message
( ]# y1 E z/ S( n7 Y. D; C1532865 CONCEPT_HDL CHECKPLUS Provide the ability for Rules Checker to report a GND symbol from the standard, and not our local library, in .mkr
0 h2 F# x4 F" i* m% n1536273 CONSTRAINT_MGR CONCEPT_HDL Model-defined differential pair is removed, and Constraint Manager Design Differences does not report an issue
4 V) R# L4 j4 O1538343 APD OTHER Inconsistent behavior when running Reports > Design Summary Report in Allegro Package Designer
+ D) i) G0 g" c1 `1539077 ALLEGRO_EDITOR SYMBOL PCB Editor crashes when choosing Layout > Renumber Pins
, p& F$ x1 k( @- M, a% e1539997 ALLEGRO_EDITOR SKILL PCB Editor crashes when the axlStringRemoveSpaces() command is run
5 d5 d* h2 n8 {' p( w+ F0 i' W$ k1541445 APD DIE_EDITOR There are two Recent Designs submenus in the APD Symbol Editor; one should be removed
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DATE: 02-12-2016 HOTFIX VERSION: 0650 O# H4 Z& p% w
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4 a9 e' a h! p1511947 ADW DSN_MIGRATION Command line arguments of the 'designmigration' command are not working4 W/ [9 B4 U7 ?; G
1517388 ALLEGRO_EDITOR SHAPE DRC error reported as PCB Editor fails to read the void for a via
5 u( L5 U# H: s7 _1521661 ALLEGRO_EDITOR PLACEMENT 'place replicate create': Automatically select etch objects connected to symbols, but not to objects outside the circuit! B$ s% j F5 ]/ j! ~+ U
1522831 APD OTHER axlSpreadsheetSetColumnProp with 'AUTO_WIDTH' propName does not autofit the contents.9 C0 c n7 d) \- g3 j3 O# M! x$ H
1524773 SIG_INTEGRITY SIMULATION Running PCB SI Probe and SigXplorer simulations show different number and shapes of waveforms- E- A2 ~! [+ h& ?, V5 M
1524875 F2B PACKAGERXL Packaging using csnetlister fails, while manual packaging of individual blocks works fine
7 m4 ?' ^# v: o+ T0 H" @- i5 }7 A1527785 SIP_LAYOUT WIREBOND SiP Layout stops responding when adding a wire to an existing finger7 b4 r; v- p, q; H8 K3 {5 v
1528479 ADW LRM LRM crashes when opened on a lower-level block in a hierarchical design
1 g8 g9 F9 P+ u, E9 w1531425 CONCEPT_HDL CORE DE-HDL crashing while trying to add a NetGroup; {+ J+ n* P e8 D1 K0 c, q
1532722 ALLEGRO_EDITOR NC Backdrill NCDrill files not getting created with PA3100 license.
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DATE: 01-29-2016 HOTFIX VERSION: 064( B) ^& t" c, P# v" e
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3 l2 L b X/ f# i1510387 FSP EXTERNAL_PORTS Break in extending a net as a deep connection when it is targeted to multiple FPGAs connected in a daisy chain
$ f* E9 v& M8 v1514132 ALLEGRO_EDITOR INTERFACES Element position changes after importing DXF. \0 o; Z7 R* S) o' @
1514285 ALLEGRO_EDITOR TECHFILE Importing .tcf file from Constraint Manager does not import user-defined properties.
0 L6 ?! b n9 |0 e1515580 ALLEGRO_EDITOR EDIT_ETCH Sliding routed differential pair signals results in odd angles if the 'Dynamic Fillets' option is selected( q7 H) |' I/ q9 s! J% @5 t6 e
1519040 ALLEGRO_EDITOR DATABASE Match groups are lost when a board created in SCM is saved in Allegro PCB Designer.
; \0 d$ J9 D. _7 G7 G1519910 CONCEPT_HDL INTERFACE_DESIGN Hotfix 62: Information on manually-remapped port groups is not saved, but reset to default
& ?) n9 n$ P7 v" Z1519943 ALLEGRO_EDITOR DATABASE When user units are changed from 4 to 2, the design seems to disappear from the canvas
, s% k& h. i# w& c: r, Q6 s1519946 CONCEPT_HDL CORE Renaming a net leads to loss of constraints associated with the net5 B N0 U& |5 a. w9 p% A/ [
1519987 ALLEGRO_EDITOR SCHEM_FTB In Hotfix 61, constraints are lost on importing a netlist% D( R- e0 j, ]% p2 S
1520727 CONCEPT_HDL CORE In Project Manager, the 'Design Sync - Export Physical' command does not automatically update the schematic4 ?7 B2 L2 ]) }0 t* ?0 K& U
1521174 SIP_LAYOUT DIE_STACK_EDITOR Padstack shapes not converted correctly to die-stack layer using Die-stack Editor) a* ]- t+ V8 m9 U# E1 J
1522227 SIP_LAYOUT IC_IO_EDITING SiP Layout stops responding when trying to add a co-design die (.xda file)0 b7 p# r: Z' C& V6 ^: |
1522900 ORBITIO ALLEGRO_SIP_IF Padstack shape distortion after translation to OrbitIO from SiP design
' t/ F4 f9 v! F+ e# C- p. K% S* r1523237 ALLEGRO_EDITOR SKILL SKILL function axlDBGetExtents() causing PCB Editor to crash. Q) W1 S. }2 m; C( D7 z }. j
1524641 ALLEGRO_EDITOR DATABASE PCB Editor stops responding when updating outdated dynamic shapes
8 l0 G+ c* ]. L& `: s9 k ^ U1525432 CONSTRAINT_MGR OTHER User-defined property not being transferred from DE-HDL to PCB Editor# j) e3 N% R0 N1 R
1525948 F2B PACKAGERXL Reference designators assigned by the Packager tool are not correct
/ {% f) g3 v0 @9 M6 E; U- h/ m% A1 ^1527321 ALLEGRO_EDITOR SCHEM_FTB Unable to create netlist with the 'Open Board in orcad PCB Editor' option in Hotfix 63
' m# P8 ^; |$ h& n$ u5 k0 F- j* C1528254 CONSTRAINT_MGR CONCEPT_HDL Import Logic with the 'Overwrite current constraints' option is deleting some attributes
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8 @0 [9 j: N; O6 E9 p! L9 jDATE: 01-15-2016 HOTFIX VERSION: 063
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& I. L' }# d6 y+ y" l1472414 ALLEGRO_EDITOR SCHEM_FTB netrev changes pin-shape spacing rule in constraint region
9 @+ l( A; u( K: j3 k1494194 CONCEPT_HDL CORE Random display of the 'PHYS_NET_NAME' property in hierarchical designs
6 O0 s3 r7 }) X* L1500190 ALLEGRO_EDITOR EDIT_ETCH Snake Router Creates Line-to-Line DRCs7 c; A# _$ u, u
1501093 SIP_LAYOUT OTHER Package design variant shows wirebonds connected to a die which is not part of the variant4 v! w4 V2 q% d D$ }. Y% q
1509184 ALLEGRO_EDITOR DATABASE BB vias in mirror have terminal pads suppressed by artwork$ c4 z& U# d+ o! O
1511397 SIP_LAYOUT TECHFILE Tech file exported from release 16.5 cannot be reused in SiP Layout in 16.5 or 16.6# T/ B, ?$ t* l2 u$ J/ O, J
1511744 ALLEGRO_EDITOR OTHER Allegro PCB Editor removes property from component instance
. t0 n2 R; z9 o/ t1511761 SIG_INTEGRITY OTHER Allegro PCB Editor crashes on running the cns_show command.1 p% V" F# n* w3 ~. [
1511787 ALLEGRO_EDITOR INTERFACES IPC-2581 not exporting overlapping shapes correctly.* R+ u( o- J4 X. }* k" S
1512071 ALLEGRO_EDITOR OTHER The color of 'SHAPE PROBLEMS' subclass is reflected in the color of 'NCLEGEND-1-4' subclass when executing PDF out/ C3 K" S# ~0 ?; G- K. e' j
1513085 CONCEPT_HDL CORE NC pins combine with NC_1 and routed as one net in Allegro PCB Editor
1 ~; H+ W! U e7 m( I0 ?! r, W1 ^, E1514469 CONCEPT_HDL CORE Unable to get rid of an underscore from the PHYS_NET_NAME property
! y2 A7 q6 _5 }# I1515318 PCB_LIBRARIAN IMPORT_EXPORT Import Pin Table: 'CTRL + C' and 'CTRL + V' not working correctly1 S; b" d" B5 p* \9 m5 h
1516093 ALLEGRO_EDITOR PADS_IN Pads library translator does not translate slot orientation* x6 `. |- c( N9 r. c
1517351 CONCEPT_HDL CORE Genview does not update an existing split symbol' L1 I# M# W. d
1518032 CONCEPT_HDL SECTION How to get rid of error 'SPCOCN-2009 - Symbol has the SEC property but the required SEC_TYPE property is missing.'
+ e6 q6 K& z1 I# A& z7 W0 S' \1518724 PCB_LIBRARIAN PTF_EDITOR PTF Editor is not saving changes) n% K6 D0 v6 }5 Z' m w
1519518 CONCEPT_HDL OTHER Genview does not generate split symbols
' y% ^8 M: h4 X+ |+ @1519623 CONCEPT_HDL CORE Differential pair added to a NetClass does not display 'NET_PHYSICAL_TYPE' on the canvas
( ?! j4 j: e8 L c6 B( G7 |4 n: [; p0 h1520207 CONCEPT_HDL CORE Genview crashes after renaming ports* B& W% g+ C4 k: ^1 E* ?
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DATE: 12-11-2015 HOTFIX VERSION: 062, b4 P4 J6 f0 _3 o
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# f7 P, H! W4 k5 v: T1012606 ALLEGRO_EDITOR REPORTS Natural sort option for Report output
% ~; C% E% ?4 N; m d% A9 G* ?8 x1408218 ALLEGRO_EDITOR MANUFACT Specifying the Offset value results in unexpected value of the NC Route coordinates in the .rou file
. k" `! f- |0 O1440509 ALLEGRO_EDITOR PLOTTING Ratsnest do not follow the refdes position when plotting the BOTTOM layer with the 'Mirror' option, d- h4 Z+ w; E6 j9 `
1444144 ALLEGRO_EDITOR DRC_CONSTR The 'add taper' command generates line to line spacing DRC; \2 n# i+ ]" l8 t
1471275 SCM UI Allegro System Architect (SCM) - Allow sorting on the pin number field in the Matrix view/ _: P4 U6 |/ M. m3 L% v
1474764 ALLEGRO_EDITOR PLACEMENT In SPB166 Hotfix 56, the place replicate create command does not produce desired results if the fanout is marked
% N9 f- k. s8 b1 O- |1474894 ALLEGRO_EDITOR PLACEMENT Place replicate fails to include vias when the module is applied to other circuits.9 t* S; \* ~' \! o/ E
1485931 ALLEGRO_EDITOR INTERFACES Errors generated when importing IDF in an existing board file
: Q( f# B; C0 H) b% O9 \1487603 SIP_LAYOUT WIREBOND SiP Layout XL - Add multibondwire option to non-standard wirebonding
, d9 t5 j1 {8 l% g8 I2 l1490311 SCM OTHER Block Packaging reports duplication when it should not3 g. t$ Q& g& O: n
1491272 ALLEGRO_EDITOR EXTRACT Incorrect information exported to DXF if the value of SeparateSlotHoleLegend is set to 'yes'" m, E# w; e: m- b# O0 J* V
1491521 F2B PACKAGERXL Packager reports error (SPCODD-269) when there are duplicate subdesign suffixes - need a clearer message) Z: d6 W, [) m# H
1492013 CONCEPT_HDL CORE Stale PNN properties not cleared from schematic on packaging design (backannotation)9 v4 L' p. D$ J/ F. p
1492703 CONCEPT_HDL OTHER 'Global Property Display' not working for symbol edit# x6 ?+ V5 u6 ^6 R1 ^. N
1495296 SIG_EXPLORER OTHER The T-point sequence in SigXplorer is different from the layout. R7 |0 r: X6 o' g4 o( D) m/ T9 d0 I3 g
1495789 ALLEGRO_MFG_OP CORE DFM checker checks for laser vias ( LVDC, LVDP, LVDT )
8 D" ^$ a, @2 S3 r. Q1496286 ALLEGRO_EDITOR PLOTTING Export PDF is not exporting hidden, phantom, and dotted line types/ n( ~" s7 B5 M& Z5 {
1499051 ALLEGRO_EDITOR PLOTTING PDF Publisher reports error for a donut shape model in the layout - 'Shape symbol cannot have a void in a shape'
0 |" l4 R: E* |( j& a2 R1499380 SIP_LAYOUT DEGASSING Oblong shape degassing voids are not created correctly' }' I9 H5 q* K7 V; j
1499538 ALLEGRO_EDITOR PAD_EDITOR Pad_designer does not allow layer name change from Begin_layer to diepad1_top; dbdoctor does not fix this
' Y- [6 v+ V7 c+ I2 L2 n1500422 ALLEGRO_EDITOR SKILL SKILL function, axlTriggerSet, results in PCB Editor crashing at launch
- ]8 [" Y( c3 R1500659 FLOWS PROJMGR Need the ability to ensure that the standard library is not added to the project libraries list by default+ d8 m5 ~! e$ F. p0 v( ]
1500725 F2B PACKAGERXL Unable to clear pstprop.dat file conflicts
8 c+ e; b& Y$ u- S9 a4 j: m- J* d1501139 ALLEGRO_EDITOR PADS_IN Pads_in creates pastemask for Through Hole padstacks; h$ X3 O. B! l9 W' X0 v
1501165 F2B DESIGNVARI TDO does not manage overlay files and variant_roz1040660_1.ba cannot be created unless variant_merged.dat is checked out
! ~6 K5 E0 u, W, ~" |1501774 ALLEGRO_EDITOR OTHER PDF Publisher: If text is attached to an object, the object is also printed in the PDF& k% H5 G3 ]4 u+ c! i6 N. ]
1501898 F2B DESIGNVARI Variant custom variables are visible in the schematic border but are not there in the Variant Details form
% N8 r% A0 {. R" }) c1501974 F2B PACKAGERXL 'Feedback has found Illegal pin swap(s)' error although the pin was already swapped and fed back (B2F) to DE-HDL
) a" ~+ I! W1 X. R2 x1502782 ALLEGRO_EDITOR SCHEM_FTB Allegro System Architect (SCM) - Export Physical stops unexpectedly without any errors or warnings- T; n% B) v) {' `
1503551 APD STREAM_IF In SPB166 Hotfix 60, error reported if a self-intersecting polygon outline exists at a specific location. m+ \% G; s3 ?
1504093 ASI_SI GUI View Topology and Waveform buttons overlap when Signal Analysis window is resized0 z( A' [3 _) Y# \
1504767 CONSTRAINT_MGR SCHEM_FTB Constraint Manager generates errors if the 'sNoF2BFlow' property is added to the Constraint Manager Dictionary
& K/ `' p, ?! m; c1 B1505497 SIP_LAYOUT LOGIC Assign net fails to fully connect propagated items l. w; `7 `0 |5 t& z
1506110 ALLEGRO_EDITOR DRC_CONSTR No DRC shown when a text on etch layer is overlapped on mechanical pin( L4 _2 f( r3 G: W5 n4 v7 r
1506654 CONCEPT_HDL INTERFACE_DESIGN Netgroups broken when moving3 s# t8 q+ f1 L9 T8 y+ M
1506983 ALLEGRO_EDITOR SKILL axlBackDrill SKILL command crashes PCB Editor after backdrill analysis is run when App mode is set to None
9 i; Z$ S6 O- T- b4 d8 N4 l0 `5 }$ ~
DATE: 11-20-2015 HOTFIX VERSION: 061+ f" _3 |5 a( g6 R& r1 [
===================================================================================================================================
# k- W; [, {, T0 [ mCCRID PRODUCT PRODUCTLEVEL2 TITLE& ]6 _; l8 h, ]5 S' F+ m
===================================================================================================================================& @ J7 y1 ?1 U+ }
1306441 APD OTHER The Minimum Shape Area option in Layer Compare uses an unspecified value, h+ F/ o& h% d7 n1 I: I! B! L% v5 ?
1342644 ADW COMPONENT_BROWSE Need directive or method for Component Browser to load a search criteria file upon init, n! Q: Q4 w; G% a# e b7 I' ~: e9 Q, X
1413248 CONCEPT_HDL CORE Import from another TDO project makes the block read-only- U4 {6 y2 ~/ e0 A8 V3 ]$ p
1417429 ALLEGRO_EDITOR INTERACTIV Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle
# \: }! c! H" L! Q( E: a2 U1417442 ALLEGRO_EDITOR INTERACTIV Spin via stack and only part of the stack spins
. q1 T2 q! j7 k3 |, l+ } D1451977 CONCEPT_HDL PDF Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set/ N0 z4 R3 b' Q. L
1453527 ALLEGRO_EDITOR EDIT_ETCH Contour route hugs the outer edge of the route keepin
% m3 e. C6 k; E8 u: j. `- q1464948 PCB_LIBRARIAN VERIFICATION The errors/warnings do not match between the various tools3 y- J; g+ I: g0 `) a
1467826 CONCEPT_HDL PDF PublishPDF from Console Window creates a long PDF filename* F" P" A# @1 A/ W* I& C' p0 u
1478639 CAPTURE OTHER Capture Browse Nets window does not display all nets
' M5 L+ c8 G" ?9 B7 r6 e: c7 K' A* I z1479177 SIP_LAYOUT OTHER Pin pair constraints do not appear to be supported in Sip Layout XL
8 J+ U( C" h0 Y; h: V3 [1479227 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy/ K6 L! Z, H6 C. U! Q) G1 _% x
1479454 CONCEPT_HDL OTHER DE-HDL issue: locked DIFF_PAIR property is editable2 u5 K7 b1 S- S7 T& b* F
1480293 CAPTURE PROJECT_MANAGER Capture hangs when searching for all nets
, P- Z& ~- L! a) z, Q: u1483894 CONCEPT_HDL CORE Import Design hangs when pull-down arrow is clicked twice$ Q2 \- J5 Y" O6 C7 K
1484781 CONCEPT_HDL CORE Three different Hierarchical Viewer issues
! H- Z8 ?' v% L. V& k( G- \1485059 PCB_LIBRARIAN CORE Part Developer pin attributes are randomly marked as read-only4 I! n I b# ^- `, N3 \7 |, s
1485960 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule is crashing the project
3 M- [( e4 @$ A! _1486086 ALLEGRO_EDITOR ARTWORK Cannot generate artwork.
* S J( C3 f3 L2 u& w" O1486834 CONSTRAINT_MGR OTHER Restore the Status column in cmDiffUtility
, R0 n2 M2 t% B2 m; f' u! d0 O1487085 CONCEPT_HDL CONSTRAINT_MGR Import Physical with the Constraints only option reports problems& @& \" J1 j* t8 Y7 L `2 [; d6 j6 X
1487197 ALLEGRO_EDITOR DRC_CONSTR Drill to Via DRCs are not being reported* v# n# E d: F- a
1487265 CONCEPT_HDL CORE Replace command in Windows mode shows incorrect behavior" u9 G7 G0 p1 s( `/ i
1487733 CONSTRAINT_MGR OTHER Running Export Physical - It takes over two hours to update the PCB Editor board
3 e. u" o3 ]' p0 n- y! ?1 p g, L3 z1488758 CONCEPT_HDL CONSTRAINT_MGR CM_VALIDATION_ON_SAVE should be a hard stop on Constraint Manager
( b C4 Z$ U" j3 |3 _; p1490299 SCM OTHER ASA does not update revision properly- g4 s9 V- X. [" f
1490744 ALLEGRO_EDITOR SKILL axlChangeLine2Cline changes line to cline and places it on the TOP layer
! t! ]0 U m+ e: C1490924 F2B PACKAGERXL Save Design/Export Physical is resetting Via constraints# M. _) H- W& x8 A
1491351 ALLEGRO_EDITOR OTHER Create Detail for bond fingers on a custom layer not working
5 _. w3 ~. ?: K* n; ]3 \1492595 ALLEGRO_EDITOR MANUFACT Dimension character substitution help is wrong
& K% _- {6 L6 r) m8 y1492777 ORBITIO ALLEGRO_SIP_IF OrbitIO import of customer mcm results in crash) b: N$ j: e2 J. a/ [0 U: P& R
1492901 CONCEPT_HDL CORE Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL
/ h/ n. Q$ ^: j1495621 ALLEGRO_EDITOR INTERFACES Oval pins are placed with wrong orientation in IPC2581
" h# T( \' ^7 ]4 r/ Q$ q: f P1497597 ALLEGRO_EDITOR DATABASE Show Element on pin shows wrong drill size0 I! q0 s( A7 n+ r
1497956 CONCEPT_HDL CORE ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root
8 F+ H( W, P1 z' O* m8 w! O% y1498234 ALLEGRO_EDITOR ARTWORK PCB Editor fails to create artwork and no error is listed in the log file' I- W5 I- W6 @$ u
1499363 CONCEPT_HDL CORE Custom attributes under variant management stopped working in Hotfix60 |
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发表于 2016-6-29 12:21
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发表于 2016-8-17 13:05