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DATE: 05-28-2016 HOTFIX VERSION: 071
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U* X6 r, h! T D$ z2 p9 j. `% I1452838 concept_HDL CORE Apparent discrepancy between Bus names and other nets
+ j; k* ^' ~7 V' Q7 `1469146 ADW LRM ERROR(SPCODD-5): Pin '1<1>' on the following primitive instance cannot be packaged in package
N, c- ]" u; g, r. D1 b1499515 ADW COMPONENT_BROWSE The Search Criteria property value is automatically being set in the ADW Component Browser$ T+ a; a7 W. Z2 V, ~: \* U
1524947 SIG_INTEGRITY SIGNOISE SI Base, PCB SI: Custom Stimulus is not recognized correctly
' o8 @2 }- z9 t; p# Q1532162 CONCEPT_HDL CORE The Rename Signal command does not update split symbols.+ |* ~$ k5 M: g% O$ F
1543997 CONSTRAINT_MGR OTHER Import Logic is overwriting the constraints in attached design.# B$ i* M( I, G ]
1544675 allegro_EDITOR OTHER Export libraries corrupts symbols if paths do not include the current directory (.)
3 T4 E7 [: B, M( d" m$ \1549097 CONSTRAINT_MGR XNET_DIFFPAIR Need to warn users creating differential pair(s) in the Physical Tab with nets that have voltage properties set% O8 C! Y0 c4 }9 t7 m
1551934 ALLEGRO_EDITOR skill axlBackDrill command is not analyzing new layer set when application mode is set to 'None'# B# {2 {1 U' W) `5 \( c z
1554919 ADW LRM LRM does not find PTF data for cell 'res' in the reference library5 h! Z7 L( j# [* E* ^9 P
1555009 CONCEPT_HDL INTERFACE_DESIGN Not possible to rename NG0 r7 D2 ^+ j; R
1557542 ALLEGRO_EDITOR OTHER DXF export creates strange result for donut-shaped polygon4 q( [$ W9 u' T+ P
1559136 ALLEGRO_EDITOR EDIT_ETCH Cannot connect floating clines to vias with nets
) I' Q7 b7 m% R# I$ ]1560301 CONCEPT_HDL CORE DE-HDL hangs when Edit menu commands are called on Linux if xclip is open
- \& X- }) i0 ]1560804 ALLEGRO_EDITOR OTHER Film records order gets reversed when using File - Import - Parameters after File - Export - Parameters2 \# u% H8 a: ?! q
1564036 CONCEPT_HDL CORE User-defined custom variables are not getting populated in the TOC
! x; Q0 l' @: K( y' j: F1564545 CONCEPT_HDL OTHER Signal model property deleted from an instance is not deleted from the instance pins. }3 P3 e" {- T4 I- o' F6 ^) K, A# p
1564552 CONCEPT_HDL CORE Find Net should zoom to the nets on schematic canvas0 ]/ _5 I( x: P3 ^1 K
1566119 CONCEPT_HDL CORE Right-clicking the schematic to add a component does not show all the schematic symbol versions9 \% I% ]' }+ W! o8 h. u7 s
1566848 ALLEGRO_EDITOR ARTWORK Board Outline artwork is incomplete2 ]' a' V; r+ [# X/ l" C
1567290 ALLEGRO_EDITOR MANUFACT Import Artwork fails to import a shape. P( H: n6 I, T/ W. A
1567587 ALLEGRO_EDITOR MANUFACT Extended tool name in header of drill file is not correct
! P- M" p' n: Q1569056 CONCEPT_HDL CORE Opening New Cascaded Window Causes Graphics Artifacts on Old Window
9 q; N, y+ X+ k" a1569087 ALLEGRO_EDITOR DRC_CONSTR Running DRC Update gives the message 'Figure outside of drawing extents. Cannot continue.'" v) a- [7 q- U/ ~
1569147 CONCEPT_HDL CORE Signal Name AutoComplete Drop Down List Not Correctly Displayed9 z' R4 e! {% K% H- w
1569924 CONCEPT_HDL CHECKPLUS ERROR (body_to_physical_check) - Pin name(s) not found in package : PEX_REFCLK0_N* PEX_REFCLK1_N*...
9 D$ @- Q0 p$ J& G: j* p0 U& }1570419 CONSTRAINT_MGR CONCEPT_HDL How do I add a customized worksheet custom property weblink in Constraint Manager4 ^; v! ?1 W( j
1570624 APD ARTWORK Artwork file has missing voids on a layer and is causing a short
G% L/ l9 o F6 G9 A1570678 F2B DESIGNVARI Variant Editor error when adding an RSTATE property* s: l2 p! h% U" u! o0 \! k% ]' P
1571113 CONSTRAINT_MGR DATABASE Reports generated from cmDiffUtility show the differences in mm units only" w1 J# o9 [9 Q- J& {2 K3 K- _
1572593 ALLEGRO_EDITOR ARTWORK ARTWORK: 'Draw holes only' option does not match display( X) W0 H9 O+ k2 I
1573205 CONCEPT_HDL CORE dsreportgen is unable to resolve the physical net names (PHYSNET)
i! ?6 D- h# x: S, E0 J1573970 CONCEPT_HDL ARCHIVER archcore fails to archive the <project CPM>.arch file; b2 `) X4 Q1 c# F% q' C: o Y- n
1574381 CONCEPT_HDL OTHER Packager crashes with some advanced settings7 o7 E2 ?7 i' |; H
1576100 ALLEGRO_EDITOR SYMBOL Update symbol crashes, creates '.sav' file, but shows update was successful in 'refresh.log'4 R+ R5 J1 K- }! j0 V
1580103 ALLEGRO_EDITOR DATABASE dbstat of 16.6 does not recognize 17.X files$ v/ d0 J& E, y- S1 l
5 u3 A2 x t/ B# g8 aDATE: 04-22-2016 HOTFIX VERSION: 069( G- n! m1 Z' i# u
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CCRID PRODUCT PRODUCTLEVEL2 TITLE3 e* X4 a* z) h' Z% y+ g/ q
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1272355 F2B DESIGNVARI Property changes on replaced component shows incorrect result in BOM output/ ]/ p) \) ~3 f& ]6 |9 u! q
1483136 ADW COMPONENT_BROWSE About searching the parenthesis or comma in Component Browser of ADW Mode3 ~) X: i/ Z. z$ x( |$ b+ l
1488909 ALLEGRO_EDITOR DRC_CONSTR Test Via causes net scheduling verification to fail. P2 a/ w. f( P- @1 t6 g" l, U$ {, u
1498389 SIP_LAYOUT DIE_GENERATOR Provide the ability in the 'die in' command to specify flip chip as a DIE symbol
0 K: |- h# e; x- O" n1506672 ALLEGRO_EDITOR INTERACTIV Replicate Place - Shapes are missing
7 T, t4 b$ d! U/ v/ s Y1523532 F2B PACKAGERXL Adding subdesign names in the "Use subdesign” or “Force subdesign" sections hangs for more than a minute% I$ O6 _% U0 B+ ]4 D
1525783 CONCEPT_HDL CORE \BASE scope does not work for SYNONYMed global signals
L4 A5 d' k( }2 j+ _. F' B% g1529846 ALLEGRO_EDITOR SHAPE Some shapes are not generated in the artwork
" H1 K9 j! |# W C7 B1537499 CONCEPT_HDL CORE Adding the same version (already placed) with the same split block name should not be allowed
$ @1 @0 @4 u- b1542334 CONCEPT_HDL CREFER creferhdl leaving lock files in sch_1 folder4 P4 S9 s. ~2 q9 }- v
1543410 ADW LRM LRM shows confusing pat status. It reports that update is needed but clicking update doesn't work) @* s$ g$ c8 w% j6 K9 ^; Q: D
1546141 ALLEGRO_EDITOR SHAPE Shapes missing from Artwork
) Y% s6 b* o6 ^' V, G+ R5 `4 ?1546877 CONCEPT_HDL CORE Align Left on Wires Fails With Incorrect Error Message
( e+ f5 J6 R" _1 e! k* h1548953 CONCEPT_HDL CORE Genview generates a symbol with strange graphics - lines going to a single point
) T* m* h- g' ^' Z+ B* W+ ]+ g1548978 ALLEGRO_EDITOR MANUFACT Shape not voiding clines# ~4 _& M7 ~1 r) u5 ]
1550941 PCB_LIBRARIAN PTF_EDITOR PDV Part Table Editor new column sorting causing problems
4 b6 b: L2 v- W" z# D1553950 ALLEGRO_EDITOR SKILL Executing axlUIControl('pixel2UserUnits) crashes Allegro U: \4 Z% {$ u- {1 y3 z, B
1554333 CONCEPT_HDL CORE Changed connectivity error when aligning ports attached to netgroups2 r' j* ~/ n5 x! U. @ [7 k
1555092 SIP_LAYOUT DEGASSING Degass offset is not working with hexagons: S$ F L/ q: N. ~/ a
1556261 ALLEGRO_EDITOR DATABASE Running DBDoctor on board file gives an error"Illegal database pointer encountered, Exiting DBDOCTOR." and crashes9 F" Y# a8 Z1 O9 R, V X) J$ F9 R) L3 |* L
1557716 APD OTHER Stream out fails with request to terminate detected - Program aborted
7 Z, v6 k" E2 o% M' O# y0 I1559951 SIP_LAYOUT SYMB_EDIT_APPMOD Wrong bump locations after Symbol Editor -> Refresh co-design die$ o# D _1 l& r
1560197 CONCEPT_HDL CORE bomhdl adds extra charcters to subdesign_suffix when generating hierarchical BOM
7 \1 k! @/ m, s. Z: ]1562537 ALLEGRO_EDITOR mentor Mentor BS to Allegro 16.6 results in Fatal Error+ E* X/ r. ?/ g; _6 h
1564203 ALLEGRO_EDITOR ARTWORK ARTWORK : Can't generate negative film.. Z% |& h1 d4 H' U
: _. `1 i" B2 |
DATE: 03-23-2016 HOTFIX VERSION: 068
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1522411 FLOWS PROJMGR License selection should persist on invoking Layout from Project Manager
, O" X" c7 F5 T1544614 ALLEGRO_EDITOR SKILL Associative dimension data reaches the 'psm' file despite deleting the layer on which it was set in the 'dra' file" T4 n9 m3 m; T4 r
1545909 ALLEGRO_EDITOR UI_FORMS Show 'microvia' checkbox in 'Blind/Buried Vias' form only with the 'Allegro_PCB_Mini' license; R% R, G) Z" S" v8 W; g; i! g
1546842 ALLEGRO_EDITOR OTHER Unsupported characters: Not being reported by 'netrev' and causing nets to short, {" s" A$ ^1 T2 m8 d( e
1547224 CONCEPT_HDL CORE Lock the 'PATH' property once it is assigned by system' ]$ Z# \- \% }1 X! `
1547584 SIP_LAYOUT OTHER SiP - Design Variant - delete embedded layer if not selected.
7 }' z& K7 Q( |1548116 CONCEPT_HDL CORE Some versions of Technology Independent Library do not appear when adding a symbol
1 V! g) d/ {( h1548151 ALLEGRO_EDITOR INTERFACES Exporting a step file gives a component rotation mismatch in the *.stp file- n* ^8 G% q: y x. @7 y) ?
1548421 F2B BOM Parts with same 'BOM_IGNORE' set do not behave the same way in the BOM report
1 c/ ^+ R. i, s# n$ V1549105 APD OTHER 'Stream out' fails with message: 'Request to terminate detected. Program aborted'% m$ V( i% J% M0 c) L
1549662 ALLEGRO_EDITOR OTHER Import parameters fails if your parampath does not have .$ @) A2 l% v, G
1549836 CONCEPT_HDL CORE Tools -> Customize -> Keys -> Reset does not actually reset keyboard shortcuts
# L/ G+ Q, g* V( n \$ O1550052 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes when copying symbols
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, r. K7 I: |$ ~DATE: 03-11-2016 HOTFIX VERSION: 0675 a5 S9 I _* j" { T% }! t
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( c3 m8 d5 j1 A; {1482953 ALLEGRO_EDITOR DATABASE Part change disassociates parts from Group
" T! U2 T$ d. a+ S0 s+ l- M+ d1484075 ALLEGRO_EDITOR pads_IN 'pads_in' imports ASSEMBLY_TOP and PLACE_BOUND_TOP outlines that are defined as shapes as lines
& Z( M/ {+ X+ t1519155 ALLEGRO_EDITOR OTHER IPC-2581-B Negative Plane Error
0 S) f: z% b n& S7 ^- V+ `9 B1528075 CONCEPT_HDL OTHER Auto Generate: DML model assignment fails with error 'There is PHYS_DES_PREFIX property in PTF file.'+ d8 R0 t# _( s* n
1528398 ALLEGRO_EDITOR SCHEM_FTB Problem with pin number format used in NC property
! c' l1 R* b C6 n% C' W+ w1529178 SIG_EXPLORER OTHER Values not transferred correctly for PinPairs when created ECSET from a net8 o" ] N. U a4 B- G; s& s2 s, A
1529720 CONCEPT_HDL COPY_PROJECT Running ADW copy project does not update the 'master.tag' file) z0 M4 `) E# T* ]* e* u- |& d
1530707 CONCEPT_HDL CORE Request to recover a 16.6 design after DE-HDL crashes
2 t0 x6 `, h, D2 P/ i0 A; v; F1532124 CONSTRAINT_MGR SCM 'File - Export - Technology file' in Constraint Manager crashes SCM if .tcf file is missing3 S" T5 M$ F3 m: v
1532788 CONSTRAINT_MGR OTHER Pin pair is hidden when Highlight Filter is ON in Constraint Manager
2 Q- c) V# q( M# Y4 \1536912 CONCEPT_HDL CORE Customizing keys in DE-HDL - Disallow mapping a command to alphanumeric characters! @. I% _" y5 R6 i/ c4 G1 J
1537055 CONCEPT_HDL CHECKPLUS Rules Checker - POWER_PINS value not obtained when schematic instance has the POWER_PINS and POWER_GROUP properties
* a, K) e8 ^$ M. [1 `) `1537278 SIG_EXPLORER SIMULATION SigXplorer (Allegro Sigrity SI) crashes when simulation is viewed in SystemSI Waveform Viewer' x8 s7 ]9 Z/ H8 L
1537339 CONCEPT_HDL INTERFACE_DESIGN No warning is flagged when moving a Net Group over a net
5 W: c! A6 F( }+ i1537521 FLOWS PROJMGR Do not allow project creation if there are spaces in directory or file names on the Linux platform
2 C1 x4 w$ l0 l1 x8 S' C! ^1539227 CONCEPT_HDL CORE Renaming a page from the hierarchy browser crashes the schematic editor.
" j: f9 e. m) Q1541532 SCM SCHGEN Generate Schematics crashes with 'Out of Memory' error
/ \$ \! i: f; y7 ]& y1541589 ALLEGRO_EDITOR INTERFACES STEP model incorrectly shown in 3D viewer. Shows pins as angled.
) M3 q$ F! R* r) @6 G1541680 CONCEPT_HDL DOC A dot (.) or period in design name created 2 separate design folders in worklib
7 w$ ^& k- U! P N' M1541687 ALLEGRO_EDITOR PADS_IN PADS closed polygons are imported as lines% |9 W7 S* x8 A5 {+ M* c0 C
1542722 ALLEGRO_EDITOR INTERFACES IDX export: RefDes and PART_NUMBER missing for mechanical symbols1 W2 l5 n/ I; A+ F! j9 O' t% F7 x
1542817 ALLEGRO_EDITOR DATABASE Import Netlist not getting completed on specific board: U5 W' w7 o) d& P& k5 P3 Q) t
1544060 SCM SCHGEN Generate Schematics causes Allegro System Architect to crash
( P- c% e3 d0 v& H0 O( r( H* Y1544633 APD STREAM_IF The 'stream out' command causes Allegro Package Designer to crash Q7 {1 B$ K$ q* ^
1544698 ALLEGRO_EDITOR PLACEMENT 'place replicate' does not add clines and vias to fanouts if fanouts are marked
5 ?5 j* {3 G4 h0 B2 j" K1544859 APD PARTITION Timing vision menu is missing in APD/SIP partitions.
# O8 Y7 H& q, o; m. _3 O/ @! L1545136 ALLEGRO_EDITOR PLACEMENT All fanouts are marked as part of one symbol instead of the symbols they attached with
1 @+ {& ?3 j2 k W9 a/ i: O9 m1545370 APD OTHER Pads in .mdd file getting placed on different layers as compared to the design
2 O, f4 g* H8 ^" v# ~* Q, s' Z6 X9 X. A3 o
DATE: 02-26-2016 HOTFIX VERSION: 066* T. J: q' f0 c. K
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5 m1 a& G# z( M! G! z, Y8 j- s1523426 ALLEGRO_EDITOR DRC_CONSTR Dynamic shape not adjusted based on keepout; DRC generated
% r) I) Z) A3 u+ K" V4 \0 n1526729 SPIF OTHER Exporting a dsn file causes PCB Editor to crash - in the interactive and batch modes: T* R2 {9 v& g r* c# F1 Z R
1529209 CONCEPT_HDL CORE When adding a component symbol version, the More option does not show all the versions( u$ _0 } o# V0 @4 g0 Z. q! G: `
1530888 ALLEGRO_EDITOR INTERFACES IPC2581 does not generate production files and fails with a segmentation fault message
4 v8 Y9 u1 T5 i8 N1532865 CONCEPT_HDL CHECKPLUS Provide the ability for Rules Checker to report a GND symbol from the standard, and not our local library, in .mkr
. t2 V6 t5 z1 D* H: t/ ~- e1536273 CONSTRAINT_MGR CONCEPT_HDL Model-defined differential pair is removed, and Constraint Manager Design Differences does not report an issue
" p" @2 D& j' u* n1538343 APD OTHER Inconsistent behavior when running Reports > Design Summary Report in Allegro Package Designer
* v8 S8 v+ N3 y9 Q( a5 i1539077 ALLEGRO_EDITOR SYMBOL PCB Editor crashes when choosing Layout > Renumber Pins& b( O0 h+ i' W! e0 o; l: o
1539997 ALLEGRO_EDITOR SKILL PCB Editor crashes when the axlStringRemoveSpaces() command is run1 Z' b! [. x# W. c
1541445 APD DIE_EDITOR There are two Recent Designs submenus in the APD Symbol Editor; one should be removed
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" l' i; B( Y$ `. X+ J" QDATE: 02-12-2016 HOTFIX VERSION: 0659 h2 w3 x/ P& g. r! H
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1511947 ADW DSN_MIGRATION Command line arguments of the 'designmigration' command are not working
: z% b8 @1 {& c* z2 \! ?) I1517388 ALLEGRO_EDITOR SHAPE DRC error reported as PCB Editor fails to read the void for a via, H# m# H* @ @7 P/ c4 q
1521661 ALLEGRO_EDITOR PLACEMENT 'place replicate create': Automatically select etch objects connected to symbols, but not to objects outside the circuit
# N1 ]. \; V2 i& x$ y5 {2 H1522831 APD OTHER axlSpreadsheetSetColumnProp with 'AUTO_WIDTH' propName does not autofit the contents.( T/ A) [7 S9 g* n A
1524773 SIG_INTEGRITY SIMULATION Running PCB SI Probe and SigXplorer simulations show different number and shapes of waveforms5 i! ~# ^! m7 O+ g
1524875 F2B PACKAGERXL Packaging using csnetlister fails, while manual packaging of individual blocks works fine
; U% m; p _& g; U1 v. K1527785 SIP_LAYOUT WIREBOND SiP Layout stops responding when adding a wire to an existing finger
3 B* O4 Q1 U8 _% Y9 K1528479 ADW LRM LRM crashes when opened on a lower-level block in a hierarchical design
% g. @, s# L9 T% x1531425 CONCEPT_HDL CORE DE-HDL crashing while trying to add a NetGroup
1 O* j. r6 a' I5 h1532722 ALLEGRO_EDITOR NC Backdrill NCDrill files not getting created with PA3100 license., }/ x5 W3 e ?( ?2 j
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DATE: 01-29-2016 HOTFIX VERSION: 064# D3 u8 I' z/ y. @* [8 |4 r
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0 }( n4 a6 I8 w( W% @$ D1510387 FSP EXTERNAL_PORTS Break in extending a net as a deep connection when it is targeted to multiple FPGAs connected in a daisy chain8 D# } g$ l1 _$ a
1514132 ALLEGRO_EDITOR INTERFACES Element position changes after importing DXF+ ]' k$ Q8 V& T0 S" ?# V, E, ]
1514285 ALLEGRO_EDITOR TECHFILE Importing .tcf file from Constraint Manager does not import user-defined properties. p2 J) Y3 Y p6 F7 ~; H
1515580 ALLEGRO_EDITOR EDIT_ETCH Sliding routed differential pair signals results in odd angles if the 'Dynamic Fillets' option is selected
2 ^4 H- T6 g2 @1 Y0 o8 n& c1519040 ALLEGRO_EDITOR DATABASE Match groups are lost when a board created in SCM is saved in Allegro PCB Designer.' n& v0 \& x8 o- ]; G$ J
1519910 CONCEPT_HDL INTERFACE_DESIGN Hotfix 62: Information on manually-remapped port groups is not saved, but reset to default
0 k( G) Z' @1 n& s8 j1519943 ALLEGRO_EDITOR DATABASE When user units are changed from 4 to 2, the design seems to disappear from the canvas
2 A- C; p+ L7 i- E% u1519946 CONCEPT_HDL CORE Renaming a net leads to loss of constraints associated with the net7 p! }( Y- @/ J0 H; e
1519987 ALLEGRO_EDITOR SCHEM_FTB In Hotfix 61, constraints are lost on importing a netlist
- e: I3 j& Z" V' `1520727 CONCEPT_HDL CORE In Project Manager, the 'Design Sync - Export Physical' command does not automatically update the schematic$ A) W ~2 k: }6 ^
1521174 SIP_LAYOUT DIE_STACK_EDITOR Padstack shapes not converted correctly to die-stack layer using Die-stack Editor
7 Y% V. h* J+ v( v1 Y1522227 SIP_LAYOUT IC_IO_EDITING SiP Layout stops responding when trying to add a co-design die (.xda file)" i' Y ?4 m# W8 W/ U9 L: ^" y: B
1522900 ORBITIO ALLEGRO_SIP_IF Padstack shape distortion after translation to OrbitIO from SiP design0 ^8 t" S. x- r% ^% _7 W& x
1523237 ALLEGRO_EDITOR SKILL SKILL function axlDBGetExtents() causing PCB Editor to crash. v" N4 ?8 @' e2 C7 I% o b- d) K
1524641 ALLEGRO_EDITOR DATABASE PCB Editor stops responding when updating outdated dynamic shapes
2 }5 f: K6 ]3 v" e: I& e1525432 CONSTRAINT_MGR OTHER User-defined property not being transferred from DE-HDL to PCB Editor4 A5 C/ `2 {! h5 Z7 T' L# J
1525948 F2B PACKAGERXL Reference designators assigned by the Packager tool are not correct
# ]# a/ ?8 a9 R; y0 i1527321 ALLEGRO_EDITOR SCHEM_FTB Unable to create netlist with the 'Open Board in orcad PCB Editor' option in Hotfix 63
9 ]+ r5 }3 u8 c1 a+ f( i( e1528254 CONSTRAINT_MGR CONCEPT_HDL Import Logic with the 'Overwrite current constraints' option is deleting some attributes
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DATE: 01-15-2016 HOTFIX VERSION: 063
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1472414 ALLEGRO_EDITOR SCHEM_FTB netrev changes pin-shape spacing rule in constraint region
; ?- d$ ~1 y) X7 o1494194 CONCEPT_HDL CORE Random display of the 'PHYS_NET_NAME' property in hierarchical designs8 v' X, I4 R. u
1500190 ALLEGRO_EDITOR EDIT_ETCH Snake Router Creates Line-to-Line DRCs
$ H" M' V8 D k+ I3 h1501093 SIP_LAYOUT OTHER Package design variant shows wirebonds connected to a die which is not part of the variant h" o7 b' j% M3 s
1509184 ALLEGRO_EDITOR DATABASE BB vias in mirror have terminal pads suppressed by artwork
4 ?/ a- }! ?0 _2 v1 `1511397 SIP_LAYOUT TECHFILE Tech file exported from release 16.5 cannot be reused in SiP Layout in 16.5 or 16.6
0 H; [$ [( }3 X6 Z+ N8 b: B/ A& ?1511744 ALLEGRO_EDITOR OTHER Allegro PCB Editor removes property from component instance) F- ` w) e) \9 F# ~8 S
1511761 SIG_INTEGRITY OTHER Allegro PCB Editor crashes on running the cns_show command.
( p: y! y- C& a3 `( o1511787 ALLEGRO_EDITOR INTERFACES IPC-2581 not exporting overlapping shapes correctly.- R! j- M+ J+ w
1512071 ALLEGRO_EDITOR OTHER The color of 'SHAPE PROBLEMS' subclass is reflected in the color of 'NCLEGEND-1-4' subclass when executing PDF out: G" J# _: N* c1 f/ N' i: ?5 E8 f
1513085 CONCEPT_HDL CORE NC pins combine with NC_1 and routed as one net in Allegro PCB Editor
) q+ S8 |6 E: e( K" a8 u1514469 CONCEPT_HDL CORE Unable to get rid of an underscore from the PHYS_NET_NAME property
& l; G: R6 I, w9 l0 {! o- L1515318 PCB_LIBRARIAN IMPORT_EXPORT Import Pin Table: 'CTRL + C' and 'CTRL + V' not working correctly
( c0 Y' A% k8 b( Q& h1516093 ALLEGRO_EDITOR PADS_IN Pads library translator does not translate slot orientation% s* |$ E& A1 i0 B% V/ l& x
1517351 CONCEPT_HDL CORE Genview does not update an existing split symbol
2 s' L: E$ L. v1518032 CONCEPT_HDL SECTION How to get rid of error 'SPCOCN-2009 - Symbol has the SEC property but the required SEC_TYPE property is missing.'; i4 q( t* ], J' u- Y6 F6 m- l
1518724 PCB_LIBRARIAN PTF_EDITOR PTF Editor is not saving changes
9 g8 z1 b4 J3 C' X d5 Y/ ?, L1519518 CONCEPT_HDL OTHER Genview does not generate split symbols
+ P( R# Q7 y3 D1519623 CONCEPT_HDL CORE Differential pair added to a NetClass does not display 'NET_PHYSICAL_TYPE' on the canvas
6 V! K- R" w8 a, F1 H8 V# R9 u1520207 CONCEPT_HDL CORE Genview crashes after renaming ports
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DATE: 12-11-2015 HOTFIX VERSION: 062( L( ^! _9 w* X+ l! I8 C
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1012606 ALLEGRO_EDITOR REPORTS Natural sort option for Report output
- v8 y0 q4 c4 ?1408218 ALLEGRO_EDITOR MANUFACT Specifying the Offset value results in unexpected value of the NC Route coordinates in the .rou file
% y+ u f5 C3 q/ A! w( c2 y& E+ L1440509 ALLEGRO_EDITOR PLOTTING Ratsnest do not follow the refdes position when plotting the BOTTOM layer with the 'Mirror' option
) q: l- n& d% o/ W& Y1444144 ALLEGRO_EDITOR DRC_CONSTR The 'add taper' command generates line to line spacing DRC
4 d4 y& |: p4 f2 s* `7 T& n1471275 SCM UI Allegro System Architect (SCM) - Allow sorting on the pin number field in the Matrix view
3 Z4 a# ?" [8 V c9 z; ~7 \ ~2 \1474764 ALLEGRO_EDITOR PLACEMENT In SPB166 Hotfix 56, the place replicate create command does not produce desired results if the fanout is marked, x/ O" _; u0 j+ C
1474894 ALLEGRO_EDITOR PLACEMENT Place replicate fails to include vias when the module is applied to other circuits.
, A$ [$ q9 o0 K% }6 D7 L# |) ?7 u1485931 ALLEGRO_EDITOR INTERFACES Errors generated when importing IDF in an existing board file$ i* ?- C6 [! f4 j2 c* Q
1487603 SIP_LAYOUT WIREBOND SiP Layout XL - Add multibondwire option to non-standard wirebonding
G6 _( j) c' U+ K1490311 SCM OTHER Block Packaging reports duplication when it should not) n Q1 J% f& N6 y
1491272 ALLEGRO_EDITOR EXTRACT Incorrect information exported to DXF if the value of SeparateSlotHoleLegend is set to 'yes'9 n$ ]$ K7 r1 H. t1 d5 Y- ]( ~
1491521 F2B PACKAGERXL Packager reports error (SPCODD-269) when there are duplicate subdesign suffixes - need a clearer message* t2 _7 a3 b) N; U2 b
1492013 CONCEPT_HDL CORE Stale PNN properties not cleared from schematic on packaging design (backannotation). q) D7 q A, C- ]. |1 H+ D( R
1492703 CONCEPT_HDL OTHER 'Global Property Display' not working for symbol edit
/ {& r! ]+ A" j: w5 u. g1495296 SIG_EXPLORER OTHER The T-point sequence in SigXplorer is different from the layout
& l! T. f% o3 s1495789 ALLEGRO_MFG_OP CORE DFM checker checks for laser vias ( LVDC, LVDP, LVDT )
& ^+ n# h: _, W7 \& I1496286 ALLEGRO_EDITOR PLOTTING Export PDF is not exporting hidden, phantom, and dotted line types
6 n% ~8 r9 H$ S" L* @- j" b5 a1499051 ALLEGRO_EDITOR PLOTTING PDF Publisher reports error for a donut shape model in the layout - 'Shape symbol cannot have a void in a shape'/ H1 I' R# i i+ S3 J* q
1499380 SIP_LAYOUT DEGASSING Oblong shape degassing voids are not created correctly0 P& y3 \4 Y! @
1499538 ALLEGRO_EDITOR PAD_EDITOR Pad_designer does not allow layer name change from Begin_layer to diepad1_top; dbdoctor does not fix this
4 R# m* N7 s& K0 I. Z0 \4 o- r1500422 ALLEGRO_EDITOR SKILL SKILL function, axlTriggerSet, results in PCB Editor crashing at launch
4 s) t: m/ [/ X6 i1500659 FLOWS PROJMGR Need the ability to ensure that the standard library is not added to the project libraries list by default/ _$ |$ w0 Y3 z V
1500725 F2B PACKAGERXL Unable to clear pstprop.dat file conflicts
`# {+ f4 i' c! N: i/ w- K1501139 ALLEGRO_EDITOR PADS_IN Pads_in creates pastemask for Through Hole padstacks/ ^. x) e2 p( Y ~3 Z
1501165 F2B DESIGNVARI TDO does not manage overlay files and variant_roz1040660_1.ba cannot be created unless variant_merged.dat is checked out2 |4 \. J( P! ]! C
1501774 ALLEGRO_EDITOR OTHER PDF Publisher: If text is attached to an object, the object is also printed in the PDF' C! ], O3 b# m$ ?7 ?
1501898 F2B DESIGNVARI Variant custom variables are visible in the schematic border but are not there in the Variant Details form. y& G& h. M% K" d0 q
1501974 F2B PACKAGERXL 'Feedback has found Illegal pin swap(s)' error although the pin was already swapped and fed back (B2F) to DE-HDL
# [ I6 v2 u$ e) V5 \- U6 I1502782 ALLEGRO_EDITOR SCHEM_FTB Allegro System Architect (SCM) - Export Physical stops unexpectedly without any errors or warnings7 r& C( ?% {% S
1503551 APD STREAM_IF In SPB166 Hotfix 60, error reported if a self-intersecting polygon outline exists at a specific location
% D4 w1 J" j( o- ]; S! k1504093 ASI_SI GUI View Topology and Waveform buttons overlap when Signal Analysis window is resized0 g5 R4 A \- X! Z9 R. n
1504767 CONSTRAINT_MGR SCHEM_FTB Constraint Manager generates errors if the 'sNoF2BFlow' property is added to the Constraint Manager Dictionary( j1 }2 w9 w1 W! Y ?) j
1505497 SIP_LAYOUT LOGIC Assign net fails to fully connect propagated items
6 z9 e& @+ S6 N0 @ F1506110 ALLEGRO_EDITOR DRC_CONSTR No DRC shown when a text on etch layer is overlapped on mechanical pin
% p! d, ]( r! F% v0 T1506654 CONCEPT_HDL INTERFACE_DESIGN Netgroups broken when moving: g, }# j% d' j; n7 m0 } e
1506983 ALLEGRO_EDITOR SKILL axlBackDrill SKILL command crashes PCB Editor after backdrill analysis is run when App mode is set to None: K3 q3 D! }# Q! j" f2 _
' s! O9 {4 I+ y& G
DATE: 11-20-2015 HOTFIX VERSION: 061
H3 o8 v5 f! }0 f===================================================================================================================================- S4 r% K D$ \! W% X9 E2 B
CCRID PRODUCT PRODUCTLEVEL2 TITLE
6 M$ r# m$ J8 o" v0 r- o===================================================================================================================================# @; W+ P3 e w. ^. n* @- [7 C
1306441 APD OTHER The Minimum Shape Area option in Layer Compare uses an unspecified value
. Z$ Y3 V( w* C: X! ?6 t+ R) n+ P% R1342644 ADW COMPONENT_BROWSE Need directive or method for Component Browser to load a search criteria file upon init( W" [. U7 T, C6 K; o
1413248 CONCEPT_HDL CORE Import from another TDO project makes the block read-only& b1 }3 |" h( u+ s" |( f9 ^
1417429 ALLEGRO_EDITOR INTERACTIV Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle
; a+ g+ n& _1 ~# F( P6 P5 ~1417442 ALLEGRO_EDITOR INTERACTIV Spin via stack and only part of the stack spins
( I; m E. ~. M1 G1 V- V0 Q' L$ [1451977 CONCEPT_HDL PDF Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set s4 ~, w) w8 L! W e; T+ `
1453527 ALLEGRO_EDITOR EDIT_ETCH Contour route hugs the outer edge of the route keepin' N- T8 h9 n$ |2 T
1464948 PCB_LIBRARIAN VERIFICATION The errors/warnings do not match between the various tools8 X7 K/ J' y: D2 D$ t3 z" O
1467826 CONCEPT_HDL PDF PublishPDF from Console Window creates a long PDF filename( K, @; B$ M) L( e
1478639 CAPTURE OTHER Capture Browse Nets window does not display all nets
% E2 [% L/ v3 h8 E1479177 SIP_LAYOUT OTHER Pin pair constraints do not appear to be supported in Sip Layout XL% m0 k+ ^8 y3 P, T: l' v. f
1479227 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy" t. \' ]* t, x9 d! Q
1479454 CONCEPT_HDL OTHER DE-HDL issue: locked DIFF_PAIR property is editable
6 A9 J# `$ h/ a1480293 CAPTURE PROJECT_MANAGER Capture hangs when searching for all nets) I- R" @, t. m C0 h$ B9 Z5 v
1483894 CONCEPT_HDL CORE Import Design hangs when pull-down arrow is clicked twice
- X. B/ F, C# n# ~6 G3 ~! r+ H1484781 CONCEPT_HDL CORE Three different Hierarchical Viewer issues
- h; [; K# i" p3 c1485059 PCB_LIBRARIAN CORE Part Developer pin attributes are randomly marked as read-only7 s ^# d. z# ~" p( R
1485960 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule is crashing the project
; l. e1 G6 M G+ ]% E) H1486086 ALLEGRO_EDITOR ARTWORK Cannot generate artwork.
0 V% s$ U) Y' [$ R5 g6 h& A* R' w1486834 CONSTRAINT_MGR OTHER Restore the Status column in cmDiffUtility0 @3 _( w, ?; n& D" m9 `/ t
1487085 CONCEPT_HDL CONSTRAINT_MGR Import Physical with the Constraints only option reports problems! u/ `- q5 c5 F; J. w4 r: e( M
1487197 ALLEGRO_EDITOR DRC_CONSTR Drill to Via DRCs are not being reported% t) o, \7 `( U" I' ]" D" i
1487265 CONCEPT_HDL CORE Replace command in Windows mode shows incorrect behavior
9 ]+ {/ V# q- Y2 [* F7 t) e1487733 CONSTRAINT_MGR OTHER Running Export Physical - It takes over two hours to update the PCB Editor board
! g' @8 G! r ?0 M1488758 CONCEPT_HDL CONSTRAINT_MGR CM_VALIDATION_ON_SAVE should be a hard stop on Constraint Manager
$ j {& h8 U8 [/ |& m! D1490299 SCM OTHER ASA does not update revision properly
) n `* i% Q" ~+ ?; W$ T1490744 ALLEGRO_EDITOR SKILL axlChangeLine2Cline changes line to cline and places it on the TOP layer
" C: |0 k; G0 Z1490924 F2B PACKAGERXL Save Design/Export Physical is resetting Via constraints
~/ l, X& c# {9 M- g2 A1 u+ v1491351 ALLEGRO_EDITOR OTHER Create Detail for bond fingers on a custom layer not working$ G" h7 y: E0 A
1492595 ALLEGRO_EDITOR MANUFACT Dimension character substitution help is wrong2 _- I: j0 B" V' |% {% c+ a8 K% F
1492777 ORBITIO ALLEGRO_SIP_IF OrbitIO import of customer mcm results in crash
! C, Z: {2 w8 I S/ ?! W1492901 CONCEPT_HDL CORE Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL9 J' K9 \/ @& b
1495621 ALLEGRO_EDITOR INTERFACES Oval pins are placed with wrong orientation in IPC2581
9 n) Z/ @" D1 M: k2 b8 x E( h" N1497597 ALLEGRO_EDITOR DATABASE Show Element on pin shows wrong drill size* Y( W/ y. R( P
1497956 CONCEPT_HDL CORE ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root m) G! H: G- d9 V, g
1498234 ALLEGRO_EDITOR ARTWORK PCB Editor fails to create artwork and no error is listed in the log file' @7 i: H1 [' k+ ?1 r' {
1499363 CONCEPT_HDL CORE Custom attributes under variant management stopped working in Hotfix60 |
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发表于 2016-6-29 12:21
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发表于 2016-8-17 13:05