Synthesiable High Performance SDRAM Contoller

Haiting32451

Synthesiable High PeRFormance SDRAM Contoller

Synthesiable High Performance SDRAM Contoller
& e% x& o+ m+ S9 D0 T# [Synchronous DRAMs are available in speed grades above 100 MHz using LVTTL I/Os. The
2 w+ W/ a- z2 F0 d. W, v+ g; aVirtex? series of FPGAs and the Spartan?-II family of FPGAs have many features, such as
) J2 v: l8 l! y- G9 U+ _SelectI/O? resource and the Clock Delay Lock Loop, that make it easy to interface to high
! A' k$ \( `, |! Ospeed Synchronous DRAMs. This application note describes the design and implementation of
a synthesizable, parameterizable, flexible, auto-placed-and-routed synchronous DRAM
controller in the Virtex FPGA family. The design can also be implemented with a Spartan-II
1 {0 x9 ^% f0 E+ V2 X7 {device. A 32-bit wide data interface version can run up to 125 MHz when automatically placed
9 D5 b: }. p! F4 o/ s6 E/ ^* gand routed in a Virtex -6 speed grade device. Hand placed versions of the design can run even
/ ^  ~3 j% E- }' ?# J2 a$ _2 Hfaster.

fish1352

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Abricy

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Hh0203

学习中，谢谢分享
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