这段文字如何理解呢？为何会进入亚稳态？

mengzhuhao

这段文字如何理解呢？为何会进入亚稳态？
3 m( _! ]2 E$ S
! T; K. u4 w( M: B- [( LIf the asynchronous reset is released at or near the active clock edge of a flip-flop, the output of the flip-flop could go metastable and thus the reset state of the ASIC could be lost.

mengzhuhao

The biggest problem with asynchronous resets is that they are asynchronous, both at the
$ ]. X; F/ q# X' O# lassertion and at the de-assertion of the reset. The assertion is a non issue, the de-assertion is the
7 J6 L+ p/ k2 B9 E3 aissue. If the asynchronous reset is released at or near the active clock edge of a flip-flop, the
output of the flip-flop could go metastable and thus the reset state of the ASIC could be lost.
, t1 ^# P* n2 t# BAnother problem that an asynchronous reset can have, depending on its source, is spurious resets
9 G2 V  \0 i  ^3 ~  G9 idue to noise or glitches on the board or system reset. See section 8.0 for a possible solution to
. B7 r- y7 V2 d  u% }# S" Kreset glitches. If this is a real problem in a system, then one might think that using synchronous
( R, N# K6 F2 g# `9 j/ A8 ^+ Fresets is the solution. A different but similar problem exists for synchronous resets if these
7 O8 _, M+ `! e7 _8 o+ Tspurious reset pulses occur near a clock edge, the flip-flops can still go metastable (but this is
true of any data input that violates setup requirements).