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http://dl.vmall.com/c0fu1auqa8" |, v, n1 O! Y0 H7 p% F$ a
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" e5 P. t; J$ A$ y( [4 S9 yDATE: 02-14-2014 HOTFIX VERSION: 023
7 K* E. s5 Q( A( q0 `. ?===================================================================================================================================
5 }1 G$ _4 M( ~( J9 ICCRID PRODUCT PRODUCTLEVEL2 TITLE& {2 i& P* j/ D6 n" r
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1120183 F2B DESIGNVARI Variant Editor Filter returns incorrect results.5 D; j' ~$ A+ m& |8 z/ q1 I
1202715 SPIF OTHER Objects loose module group attribute after Specctra: w8 K( u( y7 d. j
1203443 ADW LRM LRM takes a long time to launch for the first time. ^3 A# G5 [1 i; P/ I, R
1207204 CONCEPT_HDL CORE schematic tool crashed during save all
* k' D; {- g) O9 ?8 I4 [1222101 CONCEPT_HDL CORE Pins are shorted on a block by the Block's title delimiter0 G" e" V6 ^0 K2 Y
1223709 FSP FPGA_SUPPORT Need FSP model of Altera 5AGZME3E3H29C4 FPGA) y% c7 P5 m4 `; m
1224025 ALLEGRO_EDITOR INTERFACES The 3D viewer when working on a brd file shows package placed on BOTTOM side of my board while it is present on TOP side
; I; r6 U2 N. x1225591 F2B PACKAGERXL Aliased net signals starting with equals sign are not resolved correctly in cmgr
* f+ k! x- e6 P1226480 ALLEGRO_EDITOR EDIT_ETCH Routing time is took to double increase when using the Add Connect because DRC is Allowed., Y+ Y5 F: b7 v% S' S: b6 M
1229234 FLOWS PROJMGR Can't open the part table file from Project Setup+ ?$ f3 |, U& \& Y: m
1229555 ALLEGRO_EDITOR ARTWORK IPC-2581 not recognizing pin offsets correctly.$ M6 |& N8 L. X" p+ B" c5 l4 t. @
1229610 FSP FPGA_SUPPORT New FPGA device request - Altera Cyclone V ST: 5CSTFD6D5F31I7
) K, v/ W& D# u; z2 m7 q) p0 O4 O1229664 ALLEGRO_EDITOR SHAPE Shape not voiding different net pins causing shorts with no DRC's/ V; E3 {1 G. ?
1232601 ALLEGRO_EDITOR MANUFACT Cannot add test point to via on trace.! _0 V+ l/ t) }% y2 V$ S
1232772 ALLEGRO_EDITOR DATABASE When applying a place replicate module Allegro crashes: n: M- w% V0 C7 _$ d2 V7 T1 r
1233216 SIP_LAYOUT DIE_ABSTRACT_IF Allow more than 2 decimal places for the shrink facor in the add codesign form6 U: H( K& u; H7 S
1233690 PDN_ANALYSIS PCB_STATICIRDROP PDN IRDrop: Mesh mode in Report is incorrect.
! B: X- p( U* \$ ]& }6 O1233977 ALLEGRO_EDITOR INTERFACES single shape copied and rotated fails to create when importing IDX
, L6 Z7 \$ i# d0 h: v3 C1234357 SIP_LAYOUT SCHEMATIC_FTB DSMAIN-335: Dia file(s) error has occurred.
. \" x6 l+ ^0 u" a1234450 ALLEGRO_EDITOR INTERFACES clines, pads, etch shapes to be at the same level with the board when viewed in STEP viewer.
8 I2 T" s" t, p1 w% o6 i* ]1235587 PSPICE MODELEDITOR PSpice Model Import Wizard does not display symbol graphics for DE-HDL Symbol
; \6 a8 S) R4 k' w1236571 ALLEGRO_EDITOR GRAPHICS Allegro display lock up and panning issues
; h" w& C6 W: @* I3 ~% n1237415 ALLEGRO_EDITOR INTERFACES Multidrill pad is exported with single Drill in the STEP File
' l0 H, c& x3 M. D( Z7 I- X6 Q1237807 ALLEGRO_EDITOR SCHEM_FTB The line feed code of netview.dat |
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发表于 2014-2-18 16:44
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