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" B+ u1 e3 r. ~- ]4 uDATE: 05-24-2013 HOTFIX VERSION: 0102 @) B) f' {* V7 i5 J# n6 |
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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1 O: Z6 d: S' J( G: g# {1084716 allegro_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer
9 _2 o" R: X1 b- R/ _1111430 FSP CAPTURE_SCHEMATI Auto-resize the schematic sheet so that hierarchical block fits within border# {/ Q& d) S; v% N2 Z8 u
1119007 concept_HDL CORE PDF Publish of schematic creates extremely large PDF files
5 ?; F6 [: r& j/ b4 g- p1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor
6 K* S0 s1 I8 I- B* r- Q$ v1124610 Pspice SIMULATOR Attached design gives "INTERNAL ERROR -- OveRFlow" in SPB116.6
" U# W5 C4 W5 h. S4 X) [& {' m1125330 FSP CAPTURE_SCHEMATI FSP generates orcad schematics with components (Resistors) outside page border3 X) N. S7 R' A; ~4 J
1131775 ADW LRM LRM error with local libs & TDA) m: [ b7 R7 U- b
1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP4" k. b( t3 v4 e# h$ M8 n
1132080 ALLEGRO_EDITOR PLOTTING Size of the logo changes after File > Import > Logo
0 f7 C% p+ ^9 e1134956 SPECCTRA HIGHSPEED Route Automatic fails with error when Impedance rules are turned ON in Allegro CM.
) I# M& s. O6 T+ i1135548 SIP_LAYOUT SHAPE This design shows two areas with shape shorting errors that should not occur' W O1 [$ r5 Z6 I9 L: s- P
1138312 ALLEGRO_EDITOR MANUFACT NCROUTE is not generated for filled rectangle slot ?2 `3 G* s8 o! a" k( t& B9 E. z+ H* V1 H
1139433 ALLEGRO_EDITOR GRAPHICS embedded netnames not displayed or getting very small upon panning after exiting 3D Viewer.
- t+ x0 q1 R5 [5 R1139509 CONCEPT_HDL CORE The LRM update changes npn device to resistor1 J( q7 l8 P, d7 U6 w
1140752 ALLEGRO_EDITOR PLACEMENT Moving a place replicate module crashes allegro& Y c. |" \, W; \
1141314 SIP_LAYOUT SYMB_EDIT_APPMOD Design will lock up after changing the border using Edit Boundary in Symbol edior mode.
( y! j" W, r" w8 i1141751 ALLEGRO_EDITOR INTERFACES Allegro Crashes with Export IPC2581.: X" o l* }0 {& [4 I& J
1142478 CONSTRAINT_MGR INTERFACE_MAPPER adding constraint to netgroup causes CM & PCB SI to crash5 i* u' k, J; @, {
1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF
. y# N& s3 T$ h3 K3 ^( Q! D" M1143199 SIP_LAYOUT DIE_EDITOR Enable bump remastering, N/ I( p) ^* _
1143654 SIP_LAYOUT DIE_EDITOR Add X&Y offset when adding or moving a pin in die editor
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发表于 2013-5-25 09:24
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