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7 }5 W8 b$ e) E8 R/ n, t9 H0 P1 @I2C START / STOP Detector Verilog Code3 I3 W5 W. B2 C+ \; _/ I9 d
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module i2c_start_stop_detector (
. Y# I' r& T& I# ]: H1 n6 I Y/ D6 c input wire clk, // 系統時鐘
5 Y9 W( S" J+ ^: W+ K' P/ k input wire rst_n, // 非同步 Reset
4 b! f: E: @. ^3 U2 V* s input wire sda, // I2C 資料線
; _+ m& E: ` w input wire scl, // I2C 時鐘線
, H9 v0 E* g3 s& B9 d& U output reg start_detected, // Start 條件偵測到
& v$ h& U3 f( T% j; r, i output reg stop_detected // Stop 條件偵測到
W( q9 ~: r, j2 m# L- q);
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// 前兩個時鐘週期的 SDA 與 SCL 值0 G; I0 y0 U$ _# j9 _/ b
reg sda_d1, sda_d2;
: m4 k: u, S) x& U9 o reg scl_d1;
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m8 O2 O% j* q- W wire sda_rising = (sda_d2 == 1'b0) && (sda_d1 == 1'b1);% e0 t- R6 A% m; r, H5 W" F
wire sda_falling = (sda_d2 == 1'b1) && (sda_d1 == 1'b0);) V. \4 {6 X! W+ ^; I$ }& P$ p
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// Sample SDA and SCL
% c v3 `1 a5 } always @(posedge clk or negedge rst_n) begin( ]% u5 S8 J6 b! A# w
if (!rst_n) begin
$ Y, {5 i3 ]( a0 ~0 E. H" V sda_d1 <= 1'b1;$ [1 z1 h' a) D
sda_d2 <= 1'b1;
) m1 P8 ^8 Q5 u. ~& t; n5 \+ q$ s2 E scl_d1 <= 1'b1;
, ]7 L3 j( }1 _ u' o end else begin2 a9 H2 E! \0 d) P
sda_d2 <= sda_d1;
" ~5 X0 W% V9 q$ d$ Q4 l e sda_d1 <= sda;, }) ?4 E: o+ i" E3 w
scl_d1 <= scl;
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end8 Y5 J0 Y& Y u% H# j
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! f8 d# r9 `5 a# }# p // 偵測 Start / Stop 條件9 y/ F3 P1 u, w
always @(posedge clk or negedge rst_n) begin4 ]( X: p$ P8 k% m
if (!rst_n) begin
3 |$ d2 s! P- s- b start_detected <= 1'b0;- T4 @9 P9 A3 ], C+ d: i8 _- q- X
stop_detected <= 1'b0;
! \ N1 @8 D& k& P end else begin
2 g6 N) x6 M! ~( n/ V) @- D A // I2C START: SDA falling while SCL is high
% m, g$ N8 X; {7 M start_detected <= sda_falling && (scl_d1 == 1'b1);
1 W B( z) V+ R8 X# } // I2C STOP: SDA rising while SCL is high
! _* J" q! _/ Y0 y$ M6 K# c( T; Z stop_detected <= sda_rising && (scl_d1 == 1'b1);
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end2 m! z1 L9 ^, P/ v3 u
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endmodule
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发表于 2025-7-3 16:34
发表于 2025-7-4 18:21
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