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本帖最后由 yulizi 于 2011-12-22 11:18 编辑
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8 d% R6 w& P: u& Ghttp://kuai.xunlei.com/d/DGOHIFKLICUP
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6 x& B6 @" R4 T, |DATE: 12-16-2011 HOTFIX VERSION: 013
4 @ {3 O" }3 T5 @! {===================================================================================================================================' g* U2 o9 T7 y9 k, }, R7 K: U
CCRID PRODUCT PRODUCTLEVEL2 TITLE; o p6 {4 Y$ K4 [$ a
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" Y7 ^ z% l# A7 X/ V/ h6 J9 B875695 SIG_EXPLORER INTERACTIV Enforce Causality check box doesn't work., V$ \8 M5 @% U: c8 F9 M: w% X
927148 CAPTURE PROJECT_MANAGER Capture crashes on creating scehmatic folder with name which already exists in design
1 L$ P" L4 t. `6 U& J: ?938013 CAPTURE NETLIST_OTHER The netlist in RINF Format contained two identical lines for PCB FOOTPRINT
" M8 ]/ p2 {; m" C) a941409 Pspice PROBE BUG : Search accuracy wrong in new cursor window
0 t4 R+ Z; k/ A2 f: D945242 SIG_INTEGRITY SIMULATION Unable to select "shapes" in find filter for 'show parasitic ' command# d! H$ V# B" a& U
946293 concept_HDL ARCHIVER Archiver hangs if there is a whitespace at the end of the path of cref.dat( O/ i( F `3 c
946770 CONCEPT_HDL CORE 揤iew Design?function is missing in Windows Mode after reseting the menus.& y8 V1 e. f# b4 h6 B/ ?+ X
950994 CAPTURE NETGROUPS Problem in expanding the netgroup in Auto Connect to Bus function6 b; F! P: o+ Z: P& E0 g
953530 SIG_INTEGRITY GEOMETRY_EXTRACT Display Parasitics is displaying wrong results for EMS2D Field Solver compared to topology extraction using Probe.
0 v, ]1 g3 ?4 S1 z* ^) {' Y953713 CONCEPT_HDL PAGE_MGMT Random page replacement/duplication in block
" h) g3 I3 ?8 P d, ], I. w( J953917 CONCEPT_HDL ARCHIVER archcore should handle errors correctly
S! t: a7 ~3 v3 o& T953971 allegro_EDITOR MANUFACT NC Drill files not generated correctly when using the option "搒eparate files for plated/nonplatedholes?- }) y* d, `" h+ K/ d1 P) ]; t
954400 CAPTURE NETGROUPS BUS members of NetGroup are getting converted to Scalars in Export-Import NetGroup.8 D3 d" ` d5 E
954498 SCM B2F SCM crashes when importing physical
! W* h7 w% s$ G) p2 }/ L954623 ALLEGRO_EDITOR EDIT_ETCH Unable to complete connection with Add Connect - related to soldermask to cline check?
, `6 n1 C) [! x; d954894 ALLEGRO_EDITOR MANUFACT Dimensions disappear when opening database in v16.5 from v16.32 ^0 B D; r: f: J0 t0 Z# R
955029 CONCEPT_HDL CORE custom text font size not recognized in symbol view
! z) W8 ~2 c2 c+ K& g8 w n2 h/ F- {955133 SIG_INTEGRITY FIELD_SOLVERS The Field solver creates the differential trace model which is reversed T(D1) and T(D2) of bottom side.+ M3 R2 x: Z% Y! M. B5 n9 Y
955290 CAPTURE DRC Description for UPD0014 missing in the Browse DRC markers window. A0 U% q/ R% E) J2 Z
955299 ALLEGRO_EDITOR DRC_CONSTR drc text to smd pin does not work any more on this database in 16.3 S039( I& g7 {9 X7 @$ z0 y- g+ {: L
955338 CONCEPT_HDL CHECKPLUS Need to change PART_NAME. X8 B, x0 w, b" @9 J0 a
955447 SIG_EXPLORER OTHER Model path set in DE HDL Model Assignment not used by SigXP from CM in DE HDL
+ j# r; H# O. i6 x6 @8 }955740 SIG_INTEGRITY GEOMETRY_EXTRACT Crosstalk with Timing Windows does not work correctly
; ~! V3 r) a7 x# y955749 ALLEGRO_EDITOR MANUFACT show element Info shows symbol dimensions on incorrect subclass
# {( a& V& h0 b' {; u. H; h7 R955912 ALLEGRO_EDITOR OTHER Shapes with voids that are exported to PDF have gray filled area over the void) [3 w% p* ^. t# h' D( \0 n; Z
956129 CONCEPT_HDL INFRA DEHDL uprev hierachical design from 16.2 to 16.5 packaging failure.
- X4 Q4 q+ }, l( v956373 ALLEGRO_EDITOR NC drawing name doesn't display in the log file2 Y, F+ A) F/ @7 ~! m# R& J7 a: q
956393 CAPTURE PROJECT_MANAGER "GENERAL" and "TYPE" tabs are missing from "Properties" dialogue box.. w( D9 a7 b! h e0 Z8 |
956448 PSPICE MODELEDITOR Can not generate a DEHDL symbol from Model Editor, because no Capture license found
; E @4 B2 N2 G& o956456 CAPTURE NETLIST_OTHER OrTelesis netlist not transferring user properties defined under combined, n9 g4 @' o8 n. ~8 @ R
956489 ALLEGRO_EDITOR MANUFACT dimensions lost when symbol with diemnsions attached to symbol origin placed on board) L" X6 h3 K* |4 q2 a3 b
956603 CONCEPT_HDL OTHER Part Manager "has stopped working" after changing a component5 k n+ ^) d) p/ }5 o# ]- }
956751 ALLEGRO_EDITOR ARTWORK Import Gerber command does not work correctly, p9 G |4 }+ @ S" C' X/ y4 ]! l8 [
956847 PCB_LIBRARIAN METADATA PDV - Partdeveloper symbol to function linkage broken/changed in 16.5
2 i( D; y( [4 |9 ~. O956987 CAPTURE OTHER Find from "Search toolbar" doesn't gives complete results! i- l T9 r! A+ p' B4 h
956996 CONCEPT_HDL INFRA Correction to ERROR(SPCODD-7): Following Primitive instance causes CM to empty
9 W2 b& V$ u. C/ d* O4 N957009 CAPTURE NETLIST_OTHER Problem getting database property in mentor pads PCB netlist
8 d5 z" v' e7 }0 L! }5 a2 U: X. ~957137 APD DXF_IF DXF out command dose not work correctly.
! y* b# l- Q1 Z$ K$ ~ \957167 APD GRAPHICS Highlighting for Static shape with display_nohilitefont environment variable.4 P' v& I! _1 K$ ]6 ] g
957232 SIG_INTEGRITY OTHER Allegro crash during Model Assignment.3 f- i! @* [8 \3 a: Z
957267 CONCEPT_HDL INFRA Packager Error after Import Design$ U! g6 z5 U+ M# Y4 Z
957866 SIP_LAYOUT DATABASE Cavity outline is not getting deleted from symbol file
" |' ?% o E: o# a% [958010 ALLEGRO_EDITOR REPORTS Wants the ability to extract "Batch" reports from Partition ".dpf" files.. T0 s# d6 `4 H/ Q- `! y
958252 ALLEGRO_EDITOR TESTPREP Resequence testprep with the option - Delete probes too close crashes the design
}( h! V( \ R9 O" j9 U958253 ALLEGRO_EDITOR REPORTS Shape did not have thermal relief connected to pin but unrouted nets still shows zero.9 N6 I9 @0 R7 n( t) Z
958433 ALLEGRO_EDITOR DRC_CONSTR False embedded component DRCs
% a' l# G) G* h7 f9 R958753 ALLEGRO_EDITOR SHAPE Dynamic shape is getting corrupted in 16.5
+ y+ U9 c. R. l8 d1 w9 I959011 ALLEGRO_EDITOR OTHER copy problem of via and cline* w( u" j+ {# d% Q
959101 ALLEGRO_EDITOR EXTRACT Using extracta with excluding Thermal reliefs
- _* W, Y0 b3 s+ \0 y959253 CONCEPT_HDL INFRA Design will not open$ M% h4 G4 _3 h
959299 APD MODULES Getting ERROR(SPMHDB-279) when trying to update modules placed on the Top side
1 {" o+ c: h9 L* U, R959884 CONCEPT_HDL INFRA Design Uprev/concept2cm crashes with Application Error/Out of Memory Error.* C. O( z- H0 G/ E# m( c
959909 ALLEGRO_EDITOR SCHEM_FTB Site level propflow.txt file is ignored property is transferred
: }8 Y5 \- b$ C1 O& V( k, a+ ^0 T960067 SIP_LAYOUT PLATING_BAR Creation of plating bar removes "NODRC_ETCH_OUTSIDE_KEEPIN" property from the clines.$ T9 _. r* @6 M9 B
960126 SIG_EXPLORER EXTRACTTOP Allegro PCB SI license is used automatically at Topology Extraction of Allegro Physical Viewer.
7 h* z: q) z$ |8 U# {! @960143 SIG_INTEGRITY GEOMETRY_EXTRACT Running simulation in Bus sim happened crash while enable Coulpled Via model to S parameter; n) \$ t+ P ~8 G: k1 C6 Q0 j
961349 CONCEPT_HDL HDLDIRECT Motorola designs have broken connectivity compared to 16.3; b( k+ u! N" r3 c3 R
961816 ALLEGRO_EDITOR INTERFACES Normal Export > DXF fails and offsets the pins of the BGA symbol
2 x- W9 G2 }* H6 K, O4 d2 v% w962519 SIP_LAYOUT WIREBOND Align option doesn't work for wb_tackpoint fingers |
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