PCB Designer’s si guide

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PCB Designer's SI GUIDETable of Content
  v# {  G) t% `+ h. S+ o; TBasics of SI___________________________________________________________________5
1.1 When Speed is important? _____________________________________________5
1.1.1 Acceptable Voltage and timing values ________________________________5
1.2 Signal Integrity ______________________________________________________5
5 ?7 V; G; Y2 \1.2.1 Waveform Voltage Accuracy _______________________________________5
/ H& O( S" N; {+ c. p& h1.2.2 Timing_________________________________________________________5
4 l7 L1 z9 l. b1.3 Speed of currently used logic families ____________________________________5
1.3.1 Transition Electrical Length (TEL) __________________________________6
1.3.2 Critical length ___________________________________________________6
1.3.3 What is Transmission Line? ________________________________________6
1.3.4 What is moving in a Transmission line?_______________________________6
1.3.5 Power Plane Definition____________________________________________6
6 s4 E3 v0 E  j! U& j1.3.6 The concept of Ground ____________________________________________7
- o% A9 w7 \  R9 _9 X( p1.4 STRIPLINE circuit with Electromagnetic field _____________________________7
, D) |; a9 t! |# W1.5 RLC Transmission Line Model _________________________________________8
9 [/ j/ _' ^+ T7 z# F1.5.1 What is Impedance? ______________________________________________8
# b: N0 c' S8 A- \3 }0 }1.5.2 A Practical impedance equation for microstrip _________________________8
1.5.3 What is relative dielectric constant Er? _______________________________9



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2 Interconnections for High Speed Digital Circuits _______________________________10

' n+ ?5 W+ o0 R3 k6 y5 g2.1.1 Summary______________________________________________________10
6 t3 Y9 C6 U$ V5 b; i9 L/ l2.2 Examples of dynamic inteRFacing problems _______________________________10
2.3 IC Technology and Signal Integrity _____________________________________12
2.4 Speed and distance __________________________________________________14
, ~8 Q; z  I5 \8 d2 Q2.5 Digital signals: Static interfacing _______________________________________15
2.6 Digital signals: Dynamic interfacing ____________________________________16
' W7 A- S8 q1 W* K& y4 k5 c% z/ V2.7 Review questions ___________________________________________________18
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3 Interconnection Models____________________________________________________20

3.1 Summary__________________________________________________________20
0 u, g& }8 ]* e% I0 G2 N8 k. k3.2 Reference model for interconnection analysis _____________________________20
3.3 Receiver model_____________________________________________________21
% f2 L3 g$ m5 M2 }3.4 RC interconnection model ____________________________________________23
8 s7 t. b2 H. y  }, @; z3.5 Parameters of the interconnection ______________________________________25
3.6 Refined models _____________________________________________________26
3.7 Review question ____________________________________________________28


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4 Transmission Line Models _________________________________________________31

4.1 Summary__________________________________________________________31
0 X: S( ?2 s( \4.2 Transmission line models _____________________________________________31
  r0 T  a) h3 T: _: F6 q4.3 Loss-less transmission lines ___________________________________________32
4.4 Critical Length _____________________________________________________34
: S, k. w  T2 o* X) F" K0 l4.5 Reference transmission line model______________________________________35
4.6 Line driving _______________________________________________________36
4 y: m) N! c% T: T4.7 Propagation and reflected waves _______________________________________37
4.8 A sample system____________________________________________________39
4.9 Review questions ___________________________________________________42

PCB Designer’s SI Guide Page 2 Venkata

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5 Analysis techniques _______________________________________________________45

2 d& j$ m4 _2 z1 t- X7 P5.1 Summary__________________________________________________________45
' }( x1 y2 i' \5 g! t5.2 Transmission time and skew___________________________________________45
5.3 Effects of termination resistance _______________________________________46
2 K# g5 u, c; w- W$ h/ V5.4 Lattice diagram _____________________________________________________48
: q, J, U8 L$ q3 L5.5 Examples of Real Lines ______________________________________________49
1 h5 {' |, ]$ `/ W7 ]% ~" ]9 @5 m5.6 Simulation code ____________________________________________________51
5.7 Examples of results__________________________________________________54
) i7 H1 M  c! C5 R5.8 Review questions ___________________________________________________55

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6 Design guide for interconnection ____________________________________________57

6.1 Summary__________________________________________________________57
6.2 Incident wave switching ______________________________________________57
# R* ]& ~/ n9 o6.3 Effects of capacitive loading __________________________________________58
6.4 Termination circuits _________________________________________________59
: H5 {2 ?+ u8 a. d; f6.4.1 Passive termination______________________________________________60
6.4.2 Low power termination___________________________________________61
7 ^) s7 y' r  m! M. R6.4.3 Active low power termination circuit. _______________________________61
6.5 Driving point-to-point lines ___________________________________________62
6.6 Driving bused lines __________________________________________________64
! P# W# @/ C9 C6.7 Design guidelines ___________________________________________________67
6.8 Review questions ___________________________________________________67

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Signal Integrity in Digital Circuits ___________________________________________70
7.1 Crosstalk __________________________________________________________70
7.1.1 Summary______________________________________________________70
7.2 Examples of signal integrity problems ___________________________________70
+ K5 t0 U+ \! `% Y4 o7.3 Simplified Model for Crosstalk Analysis _________________________________71
7.4 Forward and backward crosstalk _______________________________________74
7.5 Examples__________________________________________________________76
& k, E- r3 `- s# @7.6 Near-end and Far-end crosstalk ________________________________________80
8 D  O: d4 K7 Q0 S7.7 Review questions ___________________________________________________81

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8 Design Guide to Handle Crosstalk ___________________________________________85

8.1 Summary__________________________________________________________85
8.2 Effects of Crosstalk __________________________________________________85
8.3 Passive countermeasures _____________________________________________86
8.4 Active Control of Crosstalk ___________________________________________92
8.5 Review questions ___________________________________________________94

9 Ground Bounce and Switching Noise_________________________________________97

9.1 Summary__________________________________________________________97
7 ]/ ^1 N. K, u6 }, X" i/ W& ]; q9.2 The totem pole Current Spike__________________________________________97
! Z. Y  Y5 p) ?2 ]1 N9.3 Current flow in the output capacitance __________________________________100
9.4 Total Ground Bounce _______________________________________________100
6 Z: ?0 a8 {  I) B$ p0 J9.5 Review questions __________________________________________________105
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10 Design Guide for Ground & Power Distribution _____________________________107

! ?% S" D  H9 _  E+ Q, L10.1 Summary_________________________________________________________107

PCB Designer’s SI Guide Page 3 Venkata

10.2 Decoupling Capacitors ______________________________________________107
$ ], U! c* ?7 W10.3 Placement of bypass Capacitors _______________________________________113
, P2 V$ u) X9 y! I10.4 Ground and power distribution________________________________________114
( s7 B+ i/ c0 T9 v4 s) u# s10.5 Clock distribution __________________________________________________115
10.6 Review Questions __________________________________________________118
11 Laboratory Experience _________________________________________________120
9 f2 h( p: n; T+ Z0 e1 l11.1 Summary_________________________________________________________120
11.2 Aim of the experience_______________________________________________120
11.3 Generator Parameters _______________________________________________122
11.4 Cable Parameters __________________________________________________123
11.5 Mismatch at driver and at termination __________________________________124
11.6 Capacitive Load ___________________________________________________125
11.7 7. Time-domain reflectometer ________________________________________127
11.8 Driving the line with logic devices _____________________________________128
1 p! U8 @# A; e) M. ^4 P! D1 x12 SI Analysis Strategy____________________________________________________133
12.1.1 A modern high-speed design methodology must involve the at least the following: ____________________________________________________________133
& a- }7 T" d" \* |$ x5 R+ X12.2 POSSIBLE HIGH-SPEED DESIGN APPROACHES ______________________133
6 z  X" |" A. V' a12.2.1 There are two fundamental types of conditions that need to be considered for solution space analysis:__________________________________________________134
% X  F8 z2 T7 t6 p/ x3 K12.3 SOLUTION SPACE ANALYSIS _____________________________________135
12.3.1
5 o& _9 h- r! p0 TSTEP 1 — DEFINING THE INITIAL TOPOLOGY __________________135
$ n: c* |" W4 ?4 W" V  S12.3.2 STEP 2 — DEFINE MANUFACTURING TOLERANCES AND THEIR MIN/MAX VALUES ___________________________________________________135
12.3.3
* E% g4 R; e2 Z$ G3 ]STEP 3 — DEFINE THE STARTING POINT FOR DESIGN VARIANCES 136
12.3.4
3 S8 p7 e6 V1 O, YSTEP 4 — SET UP AND RUN A NUMBER OF SIMULATION CASES _136
; U# ^2 G# n/ v3 E# r# Q6 ]12.3.5 STEP 5 — EXAMINE THE SIMULATION RESULTS, IDENTIFY WHICH CASES FAILED AND WHY ____________________________________________136
12.3.6 STEP 6 — ADAPT THE TOPOLOGY AND DESIGN RULES AS APPROPRIATE _______________________________________________________137
12.3.7 STEP 7 — REPEAT STEPS 4-6 UNTIL THE TOPOLOGY CONVERGES ON A SET OF VALUES THAT PASS FOR ALL CASES ANALYZED __________137
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STEP 8 — DERIVE DESIGN RULES FOR THE TARGET CAD SYSTEM 137
12.3.9 STEP 9 — DRIVE THE CAD RULES INTO THE CAD DATABASE, AND USE THEM TO DRIVE THE PLACEMENT/ROUTING PROCESSES ___________138
12.3.10 STEP 10 — POST LAYOUT SI ANALYSIS ______________________139
12.4 CONCLUSION____________________________________________________139
7 C2 E" B8 ?$ E3 h- Z  {; W13 Glossary _____________________________________________________________141
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PCB Designer’s SI Guide Page 4Venkata