pads logic怎样对错误进行验证

fedorayang

有没有提示错误的检查

eie

在原理图中你想检查什么错误？

fedorayang

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) d. \' O5 r) A# }7 W/ ]两个不同的网络名连在一起，有些引脚没有连接，元件存在相同的流水号等等。

eie

你所说的“不同名网络”在画原理图时PADS会让你连上线吗？！ 他会自动改成同一个网络的。
引脚没连接？ 出个Reports吧，里面有个Unused项的就是了。
/ l: n( N1 ~; C0 A( ^/ [“元件存在相同的流水号”？ 你是在开玩笑吧？

ljdx

tools->compare/eco,就是，不过我很少查

eie

tools->compare/eco 是和PCB比较了，不是在原理图设计初期的检查，明白？

fedorayang

，logic没怎么用过，提出了这个白痴的问题，请原谅

ljdx

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tools->compare/eco 是和PCB比较了，不是在原理图设计初期的检查，明白？
5 m, A, G" z9 neie 发表于 2010-6-15 13:50

, h0 Z0 o0 n8 p4 _; [2 x1 S  也可以查错的，我用过，感觉不好用而已。这个是我随便拷pads例子里面的原理图，运行compare/eco后提示的错误信息PCB Net List Errors Report - previewstart.sch - Thu Jun 17 10:00:12 2010
8 @$ @% F4 M0 Z* \-------------------------------------------------------------------------
. A9 L; I) S. B7 o8 O5 KDesign to Library Part Consistency Check
, e& ]) Z- B! S) Q----------------------------------------
Part Type LED has the following gate pins that do not match to the Library part:
" A! W& i, H# i( g0 T (A K) (K A).
% i% s; M4 R" ^Non matching Part Type LED is used by the following parts:
6 j* S- _0 ]* K) @ D1 D2.
2 Y  d1 W1 X  T! t4 u
5 K5 ?  W4 @. i: d/ r2 M- USingle/Zero Pin Net Warnings
----------------------------
/ x0 e4 Z' M1 [% b# V- a2 nNet D00 has less than two pins in PCB net list file.
6 C# I: M4 E# j# vNet D01 has less than two pins in PCB net list file.
4 z* `+ A1 s4 H8 v! gNet D02 has less than two pins in PCB net list file.
( H# N% ]. ]+ U/ g& Q5 C5 D& _. GNet D03 has less than two pins in PCB net list file.
Net D04 has less than two pins in PCB net list file.
Net D05 has less than two pins in PCB net list file.
Net D06 has less than two pins in PCB net list file.
Net D07 has less than two pins in PCB net list file.
, i/ v+ n* p0 C/ a
Schematic Connectivity Errors
/ o; `/ m0 ^  ^* {' K3 ?-----------------------------
No connectivity errors or warnings.