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[Hspice仿真] True-Hspice Device模型参考手册

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发表于 2008-3-25 17:14 | 只看该作者 回帖奖励 |正序浏览 |阅读模式

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Table of Contents
. l+ O8 B6 Z: {Audience ............................................................................................. iii) \. N* q& c1 B: g) ?9 s
Related Documents ............................................................................. iii8 E! T. X) D  n6 r; ?8 [
Conventions ........................................................................................ iv% ?2 F, {. p- K
Obtaining Customer Support .............................................................. vi
7 D/ o0 U% j$ H# }" O  YOther Sources of Information ............................................................ vii4 q' s  |( h/ t; x0 B
Revision History ............................................................................... viii' E0 A( y. B0 r: D$ ^
Chapter 1 - Overview of Models ..................................................................... 1-1
1 L/ X: K' O8 p" t2 [  }Using Models to Define Netlist Elements .............................................. 1-21 P" k& _' p1 v5 S: w6 Z4 Q
Supported Models for Specific Simulators ....................................... 1-2
0 \$ K/ H. y7 x' a3 ^+ FSelecting Models .............................................................................. 1-3
5 K. Q' m/ K6 q) j5 KExample ............................................................................................ 1-3. d$ e% ~' ^0 t. y* r, g- J/ H
Chapter 2 - Using Passive Device Models....................................................... 2-1& y, B  a- x$ f4 q; H
Resistor Device Model and Equations .................................................... 2-2
6 K) V3 P) z7 n5 ?& u5 c* `3 ?Wire RC Model ................................................................................. 2-2
# s; P  [5 n4 F, j! bResistor Model Equations ................................................................. 2-5
8 v4 a+ X4 T* @  X2 HCapacitor Device Model and Equations ............................................... 2-105 l6 }" E1 J1 d( ?- v- P
Capacitance Model ......................................................................... 2-106 M. ?8 b) B+ p& y+ Q( W
Capacitor Device Equations ........................................................... 2-110 F; |" `2 w/ V: p# g1 C
Inductor Device Model and Equations ................................................. 2-14+ \& y% N6 B  _/ h. G
Inductor Core Models ..................................................................... 2-15
4 i: A  r1 m4 _! @Magnetic Core Element Outputs .................................................... 2-18
! ?2 r/ Y% d8 `' r6 y. j9 _Inductor Device Equations ............................................................. 2-19
/ a9 ~: {7 y& BJiles-Atherton Ferromagnetic Core Model ..................................... 2-21
1 i  _: o" ?3 a7 w1 m6 s( fPower Sources ....................................................................................... 2-30( E# r4 B3 U" r
Independent Sources ....................................................................... 2-306 F6 q' A* _$ i" g4 Q
Controlled Sources .......................................................................... 2-33
3 c0 M4 d6 R( zChapter 3 - Using Diodes ................................................................................. 3-1
7 Q' ~! g8 E0 H2 XDiode Types ............................................................................................ 3-2
3 G# v5 s; \# \& ~' }3 fUsing Diode Model Statements .............................................................. 3-3
, M1 ^2 o- y1 q9 nSetting Control Options .................................................................... 3-3
6 V8 o1 h* u+ r# E' bSpecifying Junction Diode Models ......................................................... 3-5
/ U7 y3 Z4 X, ~- v  hUsing the Junction Model Statement ................................................ 3-6, J: E- Z$ E5 u/ O3 e/ T. k
Using Junction Model Parameters .................................................... 3-7" ^4 _7 @. R7 W9 B, Y
Geometric Scaling for Diode Models ............................................. 3-13
8 Q# u" q" S. ^! f$ aDefining Diode Models ................................................................... 3-158 Y: t5 C6 T/ y2 u+ i. F
Determining Temperature Effects on Junction Diodes ................... 3-18
* z" x: Z" D4 w0 h# f6 n* BUsing Junction Diode Equations ........................................................... 3-21- {8 \! ?& m* f- B3 K
Using Junction DC Equations ......................................................... 3-22
" e5 @0 P) N! [3 ^% g9 lUsing Diode Capacitance Equations ............................................... 3-25
( [0 l; m5 E- [7 i% x% ^) J$ E, \2 V' RUsing Noise Equations .................................................................... 3-27! O- d& p: ^* f% P# n3 n/ n5 D- d
Temperature Compensation Equations ........................................... 3-28
- i' P  |) M- eUsing the Junction Cap Model .............................................................. 3-32
% |8 c3 I( ]7 q* j+ |Setting Juncap Model Parameters ................................................... 3-33
1 X- Y. ]( a* i, V4 R: `0 ]Theory ............................................................................................. 3-33  @( s/ p* J& |5 x6 L: K1 h- _1 Z( C
JUNCAP Model Equations ............................................................. 3-38
/ V! ~6 F" y3 J! _4 EUsing the Fowler-Nordheim Diode ...................................................... 3-465 l- l  a5 s* l9 t) Y! x& M0 x
Converting National Semiconductor Models ........................................ 3-48$ J. w: t% B) y( P; J) P
Chapter 4 - Using BJT Models ........................................................................ 4-1
5 v2 X" B3 @2 w$ j) m4 w! ^! jUsing BJT Models .................................................................................. 4-24 o, v2 p/ H2 t, E1 R9 o) u
Selecting Models ............................................................................... 4-22 Q3 l4 G1 F/ R8 Y. @: t
BJT Model Statement ............................................................................. 4-4; r4 r9 ]) B# H* M, v7 \! a
Using BJT Basic Model Parameters ................................................. 4-5
' f2 ?+ g  k8 H* o) \9 XHandling BJT Model Temperature Effects ..................................... 4-15
' P6 P* R% F# E# UBJT Device Equivalent Circuits ............................................................ 4-218 Y( ~* R1 ]( P; V/ Z
Scaling ............................................................................................. 4-21& ^  {) {0 `! T
Understanding the BJT Current Convention ................................... 4-21
% }" ?) Z. e! t2 Z( f0 d4 n' `Using BJT Equivalent Circuits ....................................................... 4-22
$ t: D. ?% u0 h+ B% sBJT Model Equations (NPN and PNP) ................................................. 4-30
9 y# Z; c" H" g  K+ |Understanding Transistor Geometry in Substrate Diodes .............. 4-30
( n. S( b; }: `# n( E! iUsing DC Model Equations ............................................................ 4-32
! P, d2 m+ @; }& x/ f/ nUsing Substrate Current Equations ................................................. 4-33; f, {6 q7 r, _  U+ X4 @
Using Base Charge Equations ......................................................... 4-34
5 R; b! }( U3 w* j  L5 |4 kUsing Variable Base Resistance Equations .................................... 4-35$ R9 n' Z; n  l" s( l
Using BJT Capacitance Equations ........................................................ 4-36
+ K, {8 N/ W) A* }6 f0 K0 dUsing Base-Emitter Capacitance Equations ................................... 4-36
. U$ d) z* A' i0 TDetermining Base Collector Capacitance ....................................... 4-38
" \& D- O9 Q/ `Using Substrate Capacitance ........................................................... 4-401 D7 l1 ]! [% y8 I, g% W; w
Defining BJT Noise Equations ............................................................. 4-42: Z/ G, N& E2 V5 M6 C
BJT Temperature Compensation Equations ......................................... 4-44
- M% r, x+ b: {Using Energy Gap Temperature Equations .................................... 4-446 D$ p0 J& O" k; ~. l
Saturation and Beta Temperature Equations, TLEV=0 or 2 ........... 4-44( c1 \  x' G- z6 v* }
Using Saturation and Temperature Equations, TLEV=1 ................ 4-46
) f) b: U: k' I' m, @- \" TUsing Saturation Temperature Equations, TLEV=3 ....................... 4-475 ]( t! H( Z' ~0 @8 D, h5 k
Using Capacitance Temperature Equations .................................... 4-49
. c% B& }) Z$ @6 x1 |Parasitic Resistor Temperature Equations ...................................... 4-51
5 K$ P. p" F6 G& k3 ]Using BJT Level=2 Temperature Equations .................................. 4-52
: w. F5 r3 g9 l' i7 ?7 c  vBJT Quasi-Saturation Model ................................................................ 4-53
5 h* {0 h  E" Z  A7 ?6 s/ J  ~Using Epitaxial Current Source Iepi ............................................... 4-55. z) G9 @& o# t. F* o7 W, W
Epitaxial Charge Storage Elements Ci and Cx ............................... 4-55
# Y5 V; |5 \8 ^2 S5 X6 KConverting National Semiconductor Models ........................................ 4-58. @! o4 F* r0 t; c# D/ a* n
VBIC Bipolar Transistor Model ........................................................... 4-60
5 X, G. P/ \" ], x/ c( [9 S  A, v6 c/ bUnderstanding the History of VBIC ............................................... 4-60
; F( R! Y+ E" X# J" j0 R% lVBIC Parameters ............................................................................ 4-61* O/ m( b; m  q' p5 J4 A, E0 A1 p; z2 U
Noise Analysis ................................................................................ 4-62
0 U) I; v1 K. o* R: k% TLevel 6 Philips Bipolar Model (MEXTRAM Level 503) ..................... 4-71
: z- U/ I" ~/ X* m5 d4 _! r. I8 WLevel 6 Element Syntax .................................................................. 4-717 m- o2 T3 _3 a, S4 t
Level 6 Model Parameters .............................................................. 4-72
- o- p$ S: v, y' @0 n! rLevel 6 Philips Bipolar Model (MEXTRAM Level 504) ..................... 4-780 b* e6 o  I. i0 r, H4 F% J9 Q
Notes ............................................................................................... 4-79
* _+ Z; r+ D$ u$ j3 ]. N9 V/ v& y9 N$ _Level 6 Model Parameters (504) ..................................................... 4-80- F  ^+ |, r- h$ o
Level 8 HiCUM Model ......................................................................... 4-94$ p; U( I1 Z. S
What is the HiCUM Model? ........................................................... 4-948 b) C3 l* |  L8 |* X3 d1 ?1 K
HiCUM Model Advantages ............................................................ 4-940 T6 M. [+ v5 ]; V0 I; ?
Avant! HiCUM Model vs. Public HiCUM Model .......................... 4-96  s# ]: G9 }* z
Model Implementation .................................................................... 4-96
5 D0 H  M! ?7 s0 nInternal Transistors ......................................................................... 4-971 Q) M0 ]- ?5 W( t( e0 O
Level 9 VBIC99 Model ...................................................................... 4-110& j+ E  M# `, G2 A% y
Element Syntax of BJT Level 9 .................................................... 4-110& L. _/ ]% Q3 G& s: K1 z: K
Effects of VBIC99 ........................................................................ 4-112$ `( a/ J, O" l6 L% _! E, i. S
Model Implementation .................................................................. 4-112
3 }/ w) e* `4 l; J* C. iExample ........................................................................................ 4-119
% U  H; a2 `* c+ AVBIC99 Notes for HSPICE Users ................................................ 4-123
- a% W: r, [7 B' U* X, L2 X6 F  k$ mLevel 10 Phillips MODELLA Bipolar Model .................................... 4-1244 L4 o$ g( F9 [: T% ^
Model Parameters ......................................................................... 4-124
$ c: S7 T4 ~$ J$ G' r* @& {Equivalent Circuits ........................................................................ 4-129
/ L# t# F1 Y  d% EDC Operating Point Output .......................................................... 4-131: _; R% ?$ O* D4 J, K
Model Equations ........................................................................... 4-1328 P& R/ f. J: D' q! Y- Z2 t
Temperature Dependence of the Parameters ................................ 4-142
8 R' f) B# b7 W- T' `2 M0 ~+ R! m, }Level 11 UCSD HBT Model .............................................................. 4-1461 Z  Y9 u+ o+ p* R* h7 J
Using the UCSD HBT Model ....................................................... 4-146
  S' P, W3 L. v$ S$ pDescription of Parameters ............................................................. 4-147* `: s6 B5 z- w
Model Equations ........................................................................... 4-152
2 s4 G( j7 R; z2 lEquivalent Circuit ......................................................................... 4-163
) W) h, ?1 i3 o( O/ c, wExample Avant! True-Hspice Model Statement ........................... 4-165+ v0 Y9 f5 o3 ?4 G, f$ u' z3 _" |
Chapter 5 - Using JFET and MESFET Models............................................. 5-1
' ^5 h) @2 l# S- _, W# a* nUnderstanding JFETs .............................................................................. 5-2( |8 j0 Z$ n& q
Specifying a Model ................................................................................. 5-31 G% p& P0 W  {: K& p4 v
Understanding the Capacitor Model ....................................................... 5-5
, ?/ k! V5 p. H! Z8 nModel Applications ........................................................................... 5-5' d, w: |. s  o9 w. s: a4 ]2 U
Control Options ................................................................................. 5-6/ @% ]5 p8 ^$ L, G1 h
JFET and MESFET Equivalent Circuits ................................................. 5-7
- _! b- b8 d( D1 K0 q9 J' {! JScaling ............................................................................................... 5-7+ s. ~+ V( @8 u9 }
Understanding JFET Current Convention ........................................ 5-7. y+ {! k  p9 l" w2 k) s
JFET Equivalent Circuits .................................................................. 5-8  k! J9 n( k6 O) p; i( A/ C3 h
JFET and MESFET Model Statements ................................................. 5-13! }0 C( w* U4 M) i; N2 C0 P" O
JFET and MESFET Model Parameters ........................................... 5-13; i( W9 {2 F/ k8 t* V
Gate Diode DC Parameters ............................................................. 5-152 X, e  Z! B  @9 N' w  ^- U( F, `
JFET and MESFET Capacitances ................................................... 5-25, Q& p0 O% e6 n2 \( r" {1 T8 \4 W
Capacitance Comparison (CAPOP=1 and CAPOP=2) ................... 5-29$ Q3 q9 A3 |" l- S- H
JFET and MESFET DC Equations ................................................. 5-31
& z3 M% ~* a" u. @JFET and MESFET Noise Models ....................................................... 5-35
: E, g. Y4 t8 M) PNoise Parameters ........................................................................... 5-35
, a, U7 J; l2 [2 H- R+ ?& eNoise Equations .............................................................................. 5-352 n+ O* T6 N  \5 s# V! I, \
Noise Summary Printout Definitions .............................................. 5-36
+ z9 s' U3 W* f! e; B' L" b+ ^JFET and MESFET Temperature Equations ........................................ 5-37
- q5 y; f. Y9 K! U; L, }: |  a, aTemperature Compensation Equations ........................................... 5-40
6 k, _7 V% l1 }. u( A* N0 F。。。。。。。。。。。
* U0 H! [% w' f& Z
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