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Fixed CCRs: SPB 17.2 HF054
' l! U/ h5 H* O8 Z. l! \/ ?6 b04-26-20198 v( @- i1 R& \) B/ E3 d- o2 j
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w: e, Q, {' F! ~1 JCCRID Product ProductLevel2 Title
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& ~7 g5 |0 L" @; c3 j1 V2060269 ADW DBEDITOR Unable to create ECAD type mixed-case schematic model attributes
) W! }/ {& E& X+ c2030086 ADW LRM Cache part_table.ptf made by LRM Update cannot be read if it has null value in key property
2 S' ^4 o+ B% |6 i6 ~( P u7 Y' B3 w1975317 ADW PART_BROWSER Space at the end of line in CDS.LIB results in zero libraries being shown in new component browser
4 T8 j; I* g" l& S& K2076340 ADW PART_BROWSER .helix folder needs to be deleted for PTF changes to take effect and to convert a design to cache$ d, K% k. M5 ~8 o" W* k
2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name
( s; a0 r) S, y( e2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design; J" U- y0 S2 A/ L* l
2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object
8 U8 V. z7 W: e D v7 [2054243 ALLEGRO_EDITOR 3D_CANVAS Plating is not shown on stacked vias in 3D canvas
1 M9 p3 k$ r4 K; @3 |2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation* n( {$ T/ ^, o2 t" F! A6 @
2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded
6 K4 n& O" g: {; v1 a2060489 ALLEGRO_EDITOR COLOR SKILL axlGlobalVisibility() issue in a partition file: VIA/SOLDERMASK_TOP subclass visibility not turned off9 v* y+ l: _0 p. Q) p. N
2072695 ALLEGRO_EDITOR COLOR Clines of colored nets not colored when 'display_nohighlight_priority' is set
) y" k2 B4 ^4 k Y. F+ B5 o# K2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone) q9 s7 a. n/ ]$ i. S% E6 U" t3 Q
2010812 ALLEGRO_EDITOR DATABASE PCB Editor STEP model offsets should follow origin movements
" z) j1 r8 R% d% l2 R! c5 r# U2011993 ALLEGRO_EDITOR DATABASE Change STEP model mapping when Symbol Origin is changed in DRA using Setup > Change Drawing Origin# u9 b, F' a4 ^( ]0 k
2051596 ALLEGRO_EDITOR DATABASE Error for unsupported property in element
7 c e" C* t4 P6 ~! O2056497 ALLEGRO_EDITOR DATABASE Place manual is slow
0 J4 L0 }9 k0 s5 x; T2 L( L2059489 ALLEGRO_EDITOR DATABASE DBDOCTOR in batch mode with argument '-check_only' detects text error
$ d1 _( `3 \4 z9 @2064268 ALLEGRO_EDITOR DATABASE PCB Editor crashes when running SKILL code% s( I( N5 ?" r, o+ f7 L
2068588 ALLEGRO_EDITOR DATABASE Crash on opening release 16.6 design in 17.2-2016
^( ~ L* p- m$ M! b2079131 ALLEGRO_EDITOR DATABASE axlChangeNet crashes PCB Editor in fast shape mode with Microsoft Visual C++ Runtime Library Error3 i( d' w- {5 l& O
2034759 ALLEGRO_EDITOR DFM Importing DFT constraints on board does not assign csets to design but shows the csets6 v" E+ @$ w& S5 {: ^7 n* }5 u
2039992 ALLEGRO_EDITOR DFM Cset is not set in Pastemask element of DFA when importing XML Constraint File. Q" U1 Y7 t8 w' z6 p6 o2 `
2046824 ALLEGRO_EDITOR EXTRACT Extracta ECL_NETWORK View reports incorrect pin layer., ]% @) C+ f" X) w- B
2048912 ALLEGRO_EDITOR IPC Running PCB Design Compare - Graphic mode reports ERROR (SPMHA1-273) 'Shape intersects with itself'
6 O4 V9 R/ o6 f7 n X2066597 ALLEGRO_EDITOR IPC Graphical compare not completed because of self-intersecting shape locations8 }2 u9 M2 F( n, s
2079719 ALLEGRO_EDITOR IPC IPC2581 import fails with error 'Failed to add (LW)POLYLINE') m! q+ @' a G" K" _, K$ D
2066229 ALLEGRO_EDITOR NC Tool code missing in backdrill NC file on choosing 'Optimize Drill Head Travel' in NC Drill
: g3 T3 Y" C# M( n- R! ~( n2070379 ALLEGRO_EDITOR NC After running backdrill some vias are shorted to other nets
) g, W6 u5 P( i$ C! w2041881 ALLEGRO_EDITOR PAD_EDITOR Difference in locations of drill in pad editor and symbol editor
: h* D$ h) C3 [4 O2058852 ALLEGRO_EDITOR PAD_EDITOR Net associations lost on refreshing vias
7 W# c2 }/ i9 `0 {4 N2061580 ALLEGRO_EDITOR PAD_EDITOR Lock Layer Span settings specified in padstack editor not reflected in PCB Editor& |2 \+ |, ]- h8 S7 w5 l/ g- l' O
2048116 ALLEGRO_EDITOR REPORTS Extracta command files not visible in Tools-->Reports when there is a space present in the textpath variable6 w6 m% e$ V! i. B0 R. f8 m+ b* a4 T
2038949 ALLEGRO_EDITOR SCHEM_FTB Netrev is slow if there is an input board file with many modified components
/ i8 g& Q& x: ?& ]( }3 K3 d2052758 ALLEGRO_EDITOR SCHEM_FTB Connectivity objects are being reported as Added and Deleted in Constraint Differences Report
& T8 B% D* r; @% h7 `5 a7 H: m7 D2066099 ALLEGRO_EDITOR SCHEM_FTB Inconsistent net names on export physical after changing net names in DE-HDL6 F. l$ T7 E7 v6 e8 ^" T7 u
2043882 ALLEGRO_EDITOR SHAPE Shapes not updated to 'Minimum aperture for gap width' in Global Dynamic Shape Parameters window- L! ]3 ~' V$ L, T
2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update! q% \7 N2 g" {% r5 G
2052063 ALLEGRO_EDITOR SHAPE Cannot import IPC2581 due to 'Shape intersects with itself' M- `5 z6 Y- Q! b5 X% t
2056478 ALLEGRO_EDITOR SHAPE Editing shape by sliding segment causes PCB Editor to fail due to 0-length segment in shape
* {. n6 w3 Y9 F/ h2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present
9 M7 E/ t# v4 s9 ]! L% ~- l2066473 ALLEGRO_EDITOR SHAPE Teardrops create strange copper shapes6 Y" n: p, F4 m; y8 `* I
2079698 ALLEGRO_EDITOR SHAPE IPC2581 import fails with error 'Shapes intersects with itself'& a/ v' l" p, v; A& z
2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in HotFix 048.* C. C9 l0 {5 G$ d: @, S
2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash; k7 P3 A9 [0 r7 S* i& O
2023755 ALLEGRO_EDITOR STEP Export STEP includes enclosure even when it is not selected.
' C8 g! \" G. M* k& s1881233 ALLEGRO_EDITOR UI_GENERAL Green/white canvas without grid when creating a board file (File - New)
@! S3 d; _1 ?& X* F1900525 ALLEGRO_EDITOR UI_GENERAL Resizing the update symbols UI causes the options to overlap and jumble up (refresh issue)5 R p3 p6 l* B2 I" L3 {! N/ M
2003861 ALLEGRO_EDITOR UI_GENERAL Same y-coordinate returned for different vertical positions when creating board outline in HotFix 048
4 A" L- P% a+ u4 a2033958 ALLEGRO_EDITOR UI_GENERAL Incorrect canvas display on creating a design from the Start page and then opening an existing design
; p6 ~. z& t" D2 Q8 t6 L3 m3 k2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog is behind canvas6 P: G; t# V" [* h1 F" @. z: \& r. U
2054429 ALLEGRO_EDITOR UI_GENERAL Editor stops responding until choosing Done after clicking Zoom by Point twice
8 u# Q7 C3 u) a2059707 ALLEGRO_EDITOR UI_GENERAL 'HTTPS' links are not shown as hyperlinks when using allegro_html
0 R2 x0 G3 W( R1 x2 r; z9 j2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden9 V6 s& B8 @4 v p# n" z
2038105 APD DRC_CONSTRAIN APD crashes on update DRC in release 16.6
# I# {( _$ }# m( f! f2050674 APD PARTITION Cannot remove C-Point from a partitioned design6 ^1 ]: u Z3 O- K
2068814 APD WIREBOND Bond wires cross on auto-separate! p/ y5 }) o: G1 P" m! L) `
1967433 CAPTURE OTHER Cannot open DSN or OPJ files by double-clicking if Capture is already open0 q$ j, U: S! ]! m% C
1967332 CONCEPT_HDL COMP_BROWSER Crash in customer environment on clicking on last row border in PIM after filtering* z$ C4 T1 F$ ~: `. Z
2001759 CONCEPT_HDL COMP_BROWSER Using Modify Component crashes Design Entry HDL
' g1 o7 a* m6 a1 _2020788 CONCEPT_HDL COMP_BROWSER Intermittent crash when clicking bottom edge of part selection table in the Modify Component window
' h7 p4 N3 C$ K* C2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved, g+ S% o) f9 G* y& s8 d0 w8 n
2013002 CONCEPT_HDL CORE Ability to regenerate Netgroup names to remove '_1' suffix
/ [/ F3 F5 {. `. u6 e2026637 CONCEPT_HDL CORE DE-HDL crashing often when launched from EDM Flow Manager
* V: l, P P! ^4 v* M2041145 CONCEPT_HDL CORE Set font size & color of netgroup names and netgroup taps& W4 L! R1 y3 n1 ~
2056743 CONCEPT_HDL CORE NetGroups appended with _1_1, some are empty, and inconsistent in DE-HDL CM and Allegro PCB Editor CM
0 e5 Y7 o5 z8 \7 k$ I2065889 CONCEPT_HDL CORE DE-HDL Modify command moves location of attached symbol properties/ v3 r+ F+ @7 k! b
2074410 CONCEPT_HDL CORE Full net connectivity not shown in Allegro PCB Editor.) t! S/ x( @: l4 o, V/ f; B
2045717 CONCEPT_HDL RF_LAYOUT_DRI The RF PCB Options is greyed out when doing Import Physical on Linux with enterprise licenses
# S* B5 y& n2 W. S1 F2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor
' I. w0 K b; W Z/ q2050521 CONSTRAINT_MGR OTHER Unexpected Xnet removal from schematic when Export to PCB Layout is executed.6 l! V. H8 f1 y, v7 ?4 a
2066270 PCB_LIBRARIAN SYMBOL_EDITOR Unable to edit note text containing comma
0 B4 t; Z7 R! I. ]7 @- N% s2069181 PCB_LIBRARIAN SYMBOL_EDITOR Pinlist window expand/collapse buttons act weird first time when invoked.
$ @" O; w; c5 s2070007 PCB_LIBRARIAN SYMBOL_EDITOR Project not found error in Symbol Editor when path contains space character
) W2 Z- P8 w$ ^* l* ?0 b2072793 PCB_LIBRARIAN SYMBOL_EDITOR Right-click menu of formatting text objects is not consistent: second and third options are swapped
4 g3 E2 g3 ?% Q6 b k6 B$ X2073138 PCB_LIBRARIAN SYMBOL_EDITOR New Symbol Editor: Do not allow duplicate properties/ X* z" c% H9 t6 S7 X+ P. a4 m
1957458 PSPICE FRONTENDPLUGI Refresh issue with Bias Display on a new design: bias value not updated
. f. x: t) k3 D4 b8 [( g [2022211 PSPICE FRONTENDPLUGI Bias Point results are not updated6 V( ?, J q6 B6 n3 o
2031058 PSPICE FRONTENDPLUGI PSpice bias values are not getting updated
+ L. g1 b- E3 P' }; A! c2038021 PSPICE FRONTENDPLUGI Bias display is not updated
; N, I2 |: g( R3 O2055274 PSPICE FRONTENDPLUGI Capture crashes on SIMSETUP OK when two projects are open# K9 O7 ^7 | B- e! |
2053432 RF_PCB OTHER Property on RF component not transferred to new design not containing the component" o( [0 q: U4 }
2003341 SCM SCHGEN Unable to generate a schematic for hierarchical blocks
0 v: f* C; ] }$ S4 ]+ `2069924 SIP_LAYOUT DIE_ABSTRACT_ Conversion from co-design die to standard die / BGA / anything else must remove floating function pins.
% r: S; r/ ]: y B4 X' j0 q x& H2067894 SIP_LAYOUT OTHER sip database size is enormous for a small component definition used in fdesign, p% q9 d( a6 ]3 w
2067987 SIP_LAYOUT OTHER Orphaned die attachment in SiP Layout cannot be removed
6 [7 K: D+ k# L7 e$ d, g e2072857 SIP_LAYOUT OTHER SiP Layout crashes when using Find by Query and choosing 'Symbols'' U* j/ m& C6 Z6 i) \
2068973 SIP_LAYOUT REPORTS SiP Layout Missing Fillet report not catching a missing fillet in HotFix 051 and 052
& ~( ]# ~( H5 ?. P- E1 i' d. c- W6 _( L2059533 SIP_LAYOUT SYMB_EDIT_APP SiP Layout: Cannot rotate bumps in Symbol Editor application mode2 \% b8 ?8 a( k" r+ a
1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error
/ A0 r$ G2 G: g; k7 m8 ~2054869 SYSTEM_CAPTURE AUTOMATION syscapUtils.tcl command cnsAutoCreateDiffPair is broken due to missing acm_code.il and acm_config.txt files1 Y" [ y' R* V x
1966488 SYSTEM_CAPTURE CANVAS_EDIT New folder rename box does not show the text typed.
/ a0 y4 }/ A5 M+ A/ ?- j9 e1814813 SYSTEM_CAPTURE COMPONENT_BRO System Capture session log should specify the CDSSITE path for the current session4 I1 A( V" r& r' i
1977673 SYSTEM_CAPTURE COMPONENT_BRO adding reference blocks through add component error when cell name matches design name
+ P1 A! D. W" P" ?' ?$ Y2027100 SYSTEM_CAPTURE COMPOSITE_FIL pstdedb.cdsz and netlist preview in System capture is not being updated when individual netlist files are written k/ B' h# l9 P0 C$ t3 j
1961274 SYSTEM_CAPTURE CONNECTIVITY_ Xnet removed during pin swapping
! ^4 m. M# _- ~ m- E& b2041879 SYSTEM_CAPTURE CONNECTIVITY_ xnets on net with only pull-up resistor7 M8 [% o/ k' H" C2 x
1889238 SYSTEM_CAPTURE COPY_PASTE Wire fails to connect during copy and paste
7 d4 ^6 Y) W- w# `1993146 SYSTEM_CAPTURE DESIGN_EXPLOR Cannot move page up by only one position# C C1 g$ Y" Q7 [& R9 o* L
1910941 SYSTEM_CAPTURE MISCELLANEOUS Parts that are not in any schematic page appear in netlsit and BOM T/ N" Y; C. ^2 c- F9 }7 A$ \
1902347 SYSTEM_CAPTURE PRINT Prints all sheets if one sheet is specified as the print range
8 B$ z- U9 K# h, B/ i* f" Q2041272 SYSTEM_CAPTURE SMART_PDF Smart pdf displays component outline when component is not de-highlighted.
3 _6 h1 g# A- v" Y0 g* N& d8 {2065768 SYSTEM_CAPTURE SMART_PDF Custom Variable in Table Object not getting passed to PDF/ P" R9 r% @( @9 P" J
1969243 SYSTEM_CAPTURE VARIANT_MANAG Export variant does not name file correctly if the filename contains a space
7 E5 q5 C% M6 T6 T5 [, y9 u1990258 SYSTEM_CAPTURE VARIANT_MANAG Cannot paste copied preferred part to multiple parts with the same part number
, D- r9 Q0 d9 y) Q0 i& E& e' k2 n: x1992250 SYSTEM_CAPTURE WORKSPACE Double-clicking a .CPM file runs System Capture but does not open project |
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