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装完还是显示052
, O( o ?% [7 a- s* ~* f: m- F8 a' EFixed CCRs: SPB 17.2 HF053
, u% }6 T; R; t, T8 ?& P5 e. y03-01-2019
) s9 M% m% {( S& z* _: v/ q) _/ v* f========================================================================================================================================================
f# W, h; v' L! s) ?CCRID Product ProductLevel2 Title+ z; q! |5 z4 @
========================================================================================================================================================' c6 G& Q" L$ n$ K
2035766 ADW DSN_MIGRATION EDM release 17.2-2016: design migration UI is cut off on right
( Q6 A4 _0 g0 m1 ^7 ?0 ~5 ?2044872 ADW PART_BROWSER Component Browser: Only one PTF file read for multiple PTF files under Part Table all referenced in master.tag8 _- c2 B- `0 X' W7 I) \7 ~7 b
2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name
g. h6 e' k/ w5 m: I8 X2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design$ {0 d: Q/ q, V6 R& h/ D9 r
2052046 ADW TDO-SHAREPOIN Joining projects is downloading 0-byte files due to SSL error0 V$ i7 Y$ \0 E
2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object
& {6 \1 b8 v& l% Z: [2047512 ALLEGRO_EDITOR 3D_CANVAS Mechanical components do not move when bending in 3D Viewer
2 q( Y* x' @9 _2048086 ALLEGRO_EDITOR 3D_CANVAS Wirebonds are not linked to diepad when component is embedded body down- J8 @( s! }0 l& C
2051277 ALLEGRO_EDITOR 3D_CANVAS 3D View Vias are Offset from Board in Z direction
3 }' {3 N+ {' n1 ^% b S, l2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation
0 }- A6 F* ]! [+ y8 g2056547 ALLEGRO_EDITOR 3D_CANVAS 3D model not shown for component with STEP file assigned+ V) F3 h2 B) F! A
2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded
% U, I* K! ^' K2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone
. q1 |9 W; ]3 h8 b1826533 ALLEGRO_EDITOR DATABASE Dyn_Thermal_Con_Type not behaving as defined in Symbol Editor after placing on PCB file.
3 z8 ~! |/ ^! ]1857282 ALLEGRO_EDITOR DATABASE PCB Editor slow when Manhattan and Path length tooltip enabled in datatip customization- s5 ^, T* m+ Z, [7 {( S5 r% Y
2052767 ALLEGRO_EDITOR DATABASE Allegro PCB Editor crashes on editing padstack
I* z: R8 w/ ^7 @! e. L1825692 ALLEGRO_EDITOR DRAFTING Dimension line text moved by Update Symbols
" m: p$ K9 m" ^- g/ M) t$ Z* V6 g1874814 ALLEGRO_EDITOR DRAFTING 'Connect Lines' does not merge overlapping lines/ j) U* ?8 l* T% I4 r4 W3 M
1874935 ALLEGRO_EDITOR DRAFTING Angular dimension text has extra spaces added before the degree symbol.3 k* a5 [; v: z2 ^) X0 g P* f2 Q
1882597 ALLEGRO_EDITOR DRAFTING 'Trim Segment' should allow trimming for all intersecting segment types
; J# z8 |# M- H3 ]8 ?2052315 ALLEGRO_EDITOR DRC_CONSTR DRC (pad-shape) incorrect when both pad and drill are offset from pad origin.
( d" N/ u. ~5 O$ r2040603 ALLEGRO_EDITOR EDIT_SHAPE Shape is not updating correctly after the 'move' command. I2 Q0 J% }0 s$ @5 Y
2050177 ALLEGRO_EDITOR INTERACTIV Letters need to remain aligned and uniform after performing Boolean ANDNOT operation
9 e: W6 _. h# ^7 d2052586 ALLEGRO_EDITOR IPC IPC356 showing shorts and disconnects for chip-on-board design" u" t9 j# j% s- z, Z; F
2044350 ALLEGRO_EDITOR MANUFACT Cross Section table showing multiple decimal digits for the Tolerance column0 L. r4 j+ a# {1 D6 k8 d
2051150 ALLEGRO_EDITOR NC Counterbore/Countersink holes not being shown in the NC legend table.
$ n) i9 w; A% y$ Y1 ]2058199 ALLEGRO_EDITOR NC 'Manufacture - NC - Drill Legend' does not populate the CounterBore/CounterSink row values in the Drill Chart table
9 }2 k$ ?/ N% b; a! c* d! X+ P2061809 ALLEGRO_EDITOR NC Counter bore NC Legend does not show any data
# u8 O6 x" f' X/ q% o" u2063477 ALLEGRO_EDITOR NC Counter bore NC Legend does not show its value- g* Z) G/ S" | F$ v: D! O; d% a
2033849 ALLEGRO_EDITOR PLACEMENT PCB Editor stops responding when removing a plane that the Place Replicate command added
% k9 \7 ]! e/ w" K& {7 X2037509 ALLEGRO_EDITOR PLACEMENT Move or Rotate or Mirror of a module/group makes PCB Editor to crash with no .SAV file created
2 P* \" [4 F* k2047480 ALLEGRO_EDITOR SCHEM_FTB Importing netlist using Capture-CM flow in PCB Editor is crashing netrev
6 v. n- m A" L; `6 f2046276 ALLEGRO_EDITOR SHAPE Add notch is not snapping to the grid point
+ t+ P' r! R0 U4 P& W2047572 ALLEGRO_EDITOR SHAPE Voiding elements on static shape do not void adjacent layer keep-outs and PCB Editor stops responding
! S, l- j0 h% {& n' L2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update
/ h' D" k% c+ f) o2050120 ALLEGRO_EDITOR SHAPE Dynamic fill is flooding over other etch shapes within a symbol.
( v$ f- w4 ]8 O9 Y* h# x1 T& D2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present
' `3 B8 d0 {/ p. G2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in hotfix 048.
3 q0 h$ ~, T) k: \- j/ \7 y2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash/ [9 s8 C1 ~1 [+ Q k! U, f2 r+ m; Y
1961689 ALLEGRO_EDITOR SYMBOL Pin Numbers are moved from center with Pin Rotation when adding pins to Footprint
1 _8 G! J- C+ S8 n; a( V, @2034949 ALLEGRO_EDITOR SYMBOL Angular dimension from DRA not created in PCB) a$ ?; o( d$ q8 J. p! B
2046242 ALLEGRO_EDITOR UI_GENERAL Searching User Preference Summary results in crash
5 c& j0 a. i( q; u) _2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog box is behind canvas
( q. O9 ]0 H! p" R& Q; e8 ^" c, ~2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden/ c2 }# M1 @, Z. P& W+ X- P1 ^4 u
1886781 ALLEGRO_VIEWER OTHER Opening Color192 in Allegro Free Viewer causes it to crash
4 \, X1 j7 G/ g7 X- U; P, j1699433 APD EDIT_ETCH Field solver runs when not expected( ?' }: ?: w/ K9 x8 f }" P+ }% |
1937159 APD EDIT_ETCH Routing clines takes long time5 z2 C5 N! Y# y% z& s, G/ C
2050863 APD SHAPE Taper voiding process is different in Within the region/Out of Region8 ^/ N E8 V M9 y" q! w2 c2 P
2047391 CAPTURE PART_EDITOR Pin type cannot be changed in hotfix 051
( H& l/ D/ O: ~6 A2049161 CAP_EDIF IMPORT Fatal error 'cannot determine grid' when converting third-party design to Capture1 t, g8 ]- f1 M( V
2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved8 z7 v$ O: i. i4 Q
2047583 CONCEPT_HDL COPY_PROJECT Design Entry HDL crashing when trying to open page 52 of copied project" [- C, ?" n. X1 {* V$ p
2036239 CONCEPT_HDL CORE When cutting/pasting, multiple error pop-ups appear for the same notification: N. X, q) B4 f# p, v" }% ~2 R
2037572 CONCEPT_HDL CORE Warning (SPCOCD-578): Soft VOLTAGE property found is misleading and should be auto resolved when closing CM
1 G% }$ d0 k- |. D2037578 CONCEPT_HDL CORE VOLTAGE property gets deleted after copying it from a non-synchronized source
+ h/ A5 T4 p" e$ P# p0 C8 J2046958 CONCEPT_HDL CORE Moving block pins from symbol right to left places pin names outside the symbol
# @/ _) `8 Z$ k! m7 N, c* A2032480 CONSTRAINT_MGR CONCEPT_HDL Incorrect matchgroups created when working with multiple level nested hierarchical blocks
( h N( N9 s* }9 Z( w2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor8 ]4 ]# A. ~& G, e$ ~- G
2046765 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout 'dump libraries' crashes when exporting library3 l" \# j; V8 d/ E2 Y
2067970 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout cannot dump libraries, viewlog is empty
% t% ~# @3 K) g/ x! K7 o) F2 q: r1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error' d; b: A* w. z# M" w" T) U
1968437 SYSTEM_CAPTURE ASSIGN_SIGNAL Net name pasted in lower-case though UPPERCASE INPUT is enabled+ T7 k1 Z3 `/ q1 h# x' ^: T! o* A
1983063 SYSTEM_CAPTURE AUTOSHAPES Auto Shapes are being shown as part of components. y _8 T1 F( ~5 I( S# n3 T
1968463 SYSTEM_CAPTURE CANVAS_EDIT System Capture should not allow illegal characters to be entered for net names
9 C* g5 r& \3 Y! q/ f( b2006593 SYSTEM_CAPTURE CANVAS_EDIT Asterisk in a search string is not treated as a wildcard character
; T, M; v4 s0 H m8 K9 v1721863 SYSTEM_CAPTURE CONNECTIVITY_ Net Names move to random locations when the components are moved around the canvas
G/ M. F9 u" r/ I/ l5 Q1 z1960130 SYSTEM_CAPTURE CONNECTIVITY_ Disconnected nets when using the mirror option
j- \( ]: v5 |6 u1985029 SYSTEM_CAPTURE EDIT_OPERATIO Net aliases do not drag with circuit, they appear to move after the circuit is dropped
* x& b+ ~. Q8 U \! E1895142 SYSTEM_CAPTURE EXPORT_PCB System Capture reports incorrect unsaved changes when closed after running export physical; P7 w( ?3 E, ~; U( @! \5 C( e
1628596 SYSTEM_CAPTURE FIND_REPLACE Alias issue in Find: Results do not show the resolved physical net names
- L3 U8 f E3 p3 {0 \ n1988297 SYSTEM_CAPTURE FIND_REPLACE Edit > Find and Replace does not replace a net with an existing net on the canvas
I3 Z6 P, i/ ~ W% r7 m$ _6 o3 U1843885 SYSTEM_CAPTURE FORMAT_OBJECT Renaming a net causes it to lose custom color assignment
9 U# d2 t9 L8 k6 k; |: R1969308 SYSTEM_CAPTURE FORMAT_OBJECT System Capture: Clicking arrows to increase/decrease font size does not work correctly when clicked fast1 I8 n' A; m# m; J2 k
1990060 SYSTEM_CAPTURE FORMAT_OBJECT Bold, italics, and underline formats not visually shown on all selected objects concurrently0 E% M% ]% V5 ]4 w8 ~; k
1993208 SYSTEM_CAPTURE FORMAT_OBJECT Setting font prior to placing text does not work, pop-up does not work, and bucket results in scrolling page
- j$ R: d2 _& d1981775 SYSTEM_CAPTURE IMPORT_PCB Import Physical takes a long time on some designs to launch the UI f$ ?; r' F, e
1982320 SYSTEM_CAPTURE IMPORT_PCB In the B2F flow none of the *view files are created
' J9 D, \+ e A' k- X2 v2010996 SYSTEM_CAPTURE INSERT_PICTUR Image in title block is at a wrong location in design: correctly placed in library
z# ~( D* |1 `4 W1967614 SYSTEM_CAPTURE MISCELLANEOUS Dragging a circuit with net aliases does not move the net aliases with it
, U1 E2 f ]' Z+ M; H1980999 SYSTEM_CAPTURE NEW_PROJECT System Capture stops working with message regarding Part Manager initialization for a design based on DE-HDL3 Z: k: |/ g1 z* Z, m" b
1973437 SYSTEM_CAPTURE OPEN_CLOSE_PR Opening a design crashes System Capture# [. i4 f8 t. {" Y* ^! ?
1986566 SYSTEM_CAPTURE OPEN_CLOSE_PR System Captures stops responding on opening project, cleaning project displays project already open message
( V/ K* V Q: w M1993093 SYSTEM_CAPTURE OPEN_CLOSE_PR Add option to override the lock file similar to Allegro PCB Editor8 X2 z# g; a9 m8 A
2042360 SYSTEM_CAPTURE OPEN_CLOSE_PR System Capture will not open nor gives error message when previous lock file present inside the logic folder `' \/ N0 o6 z P$ ~
1992247 SYSTEM_CAPTURE PART_MANAGER Part Manager displays message for undo and redo stack even after specifying not to show message
8 M6 S/ i: h; N1 ~2048000 SYSTEM_CAPTURE PERFORMANCE Performance issue when instantiating and moving a component
3 R3 v: p* u; g3 H4 h1892120 SYSTEM_CAPTURE PROPERTY_EDIT Some parts missing reference designators and some have two properties, RefDes and REFDES, C7 D/ U" X" N) s) Q
1970009 SYSTEM_CAPTURE PROPERTY_EDIT System Capture: Right-clicking RefDes with conflict in 'Edit Properties' shows the Hyperlink option
; }" ?' u! t/ ]: Y% F2042707 SYSTEM_CAPTURE VARIANT_MANAG variant.lst file under 'physical' folder not updated when closing Variant Editor+ l6 r! N4 t! K2 U
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发表于 2019-4-6 21:51
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