【新】ADAPTIVE FILTER ARCHITECTURES FOR FPGA IMPLEMENTATION

Wenghezhong

1 Introduction
$ l1 l1 U. }+ ]6 Z. e& S! ~3 b5 I1.1 Purpose.................................................................................................................. 1
6 C6 C8 _9 @- o/ n4 X+ F: k1.2 Overview............................................................................................................... 1
  x7 _# P0 g, L7 O1.2.1 Advantages of DSP..................................................................................... 2
+ ]" ?5 p' k! b% O1.2.2 Reconfigurable Hardware Advantages ................................................... 2
/ t7 Q/ ?; w' C. n1 o1.3 Organization of Thesis ........................................................................................ 3
; Q! y1 J: j( e# c& z2 Programmable Logic Devices
* `2 n5 e) F, w+ B. p  _7 |2.1 History of Programmable Logic ......................................................................... 4
9 m9 ~' Z3 K3 t' d2.2 FPGA Architecture................................................................................................ 6
2 h1 i$ h. ?1 h$ n2 V1 v9 `2.3 Device Configuration ........................................................................................... 9
5 q! h. M9 F/ e% c2.3.1 Schematic Design Entry .............................................................................. 9
2.3.2 Hardware Description Languages ............................................................11
2.3.3 High‐Level Languages ................................................................................11
5 L# L% L7 ?8 d/ W- b2.4 Current Trends ......................................................................................................12
5 G+ A8 G5 T( D: p) I3 m3 Adaptive Filter Overview
3.1 Introduction .......................................................................................................... 13
' @% \, E) Z* J4 N# q& z9 _6 G6 X3.2 Adaptive Filtering Problem................................................................................ 14
3.3 Applications.......................................................................................................... 15
& F" g$ o6 i6 |1 S! Q3.4 Adaptive Algorithms........................................................................................... 16
, }1 W; d1 b9 k7 P/ y# G/ W6 @+ }3.4.1 Wiener Filters............................................................................................... 17
3.4.2 Method of Steepest Descent ...................................................................... 19
3.4.3 Least Mean Square Algorithm .................................................................. 20
3.4.4 Recursive Least Squares Algorithm ......................................................... 21
& L( N# Z8 O4 G4 FPGA Implementation
/ h$ T- C; w* F. F4.1 FPGA Realization Issues ..................................................................................... 23
5 c4 e  M$ `3 f  _* t3 z: V( E4.2 Finite Precision Effects ........................................................................................ 24
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5 H* i4 b3 E" A; G) c4.2.1 Scale Factor Adjustment............................................................................. 24
4.2.2 Training Algorithm Modification............................................................. 27
1 U7 H- |! r. e( y4.3 Loadable Coefficient Filter Taps........................................................................ 31
4.3.1 Computed Partial Products Multiplication............................................. 31
4.3.2 Embedded Multipliers ............................................................................... 34
4.3.3 Tap Implementation Results ..................................................................... 34
4.4 Embedded Microprocessor Utilization............................................................. 37
4 `) X( J, l& Z* z# z4.4.1 IBM PowerPC 405 ....................................................................................... 37
4.4.2 Embedded Development Kit..................................................................... 38
4.4.3 Xilinx Processor Soft IP .............................................................................. 38
4.4.3.1 User IP Cores ................................................................................... 39
: X, V" R# p' x" f. t2 c& [4.4.4 Adaptive Filter IP Core .............................................................................. 41
5 Results
5.1 Methods Used....................................................................................................... 42
. C5 T" \+ Z3 f# e8 _8 h9 i5.2 Algorithm Analyses............................................................................................. 44
, f3 o) h: N" A" M: F- \) `* Q5.2.1 Full Precision Analysis............................................................................... 44
5.2.2 Fixed‐Point Analysis................................................................................... 46
" ^& p) d- Q1 d: f5.3 Hardware Verification......................................................................................... 48
8 T3 A( B6 e" a8 v# ?2 T5.4 Power Consumption............................................................................................ 49
. l; m* t, l+ k, M; Z" z' k5.5 Bandwidth Considerations................................................................................. 50
6 Conclusions
6.1 Conclusions........................................................................................................... 52
* ?2 M+ Y" r' ^' R; r6.2 Future Work.......................................................................................................... 53
Appendix A Matlab Code........................................................................................... 55
Appendix B VHDL Code............................................................................................ 59
! t) d  `) h2 O; Q* nAppendix C C Code .................................................................................................... 75
Appendix D Device Synthesis Results ................................................................... 80
References ..................................................................................................................... 83
% N, W) w% A8 U( ^. _, MBiographical Sketch .................................................................................................... 86

hasky

学习了!3Q
% E6 `0 O( B/ e" f1 R! b6 n

Gegu

非常感谢，收了！
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