Synthesiable High Performance SDRAM Contoller

Haiting32451

Synthesiable High PeRFormance SDRAM Contoller
. v1 n: Z' G; G& f! w; d. G
Synthesiable High Performance SDRAM Contoller
9 q- j  ^% B3 U; t+ b9 p4 F) kSynchronous DRAMs are available in speed grades above 100 MHz using LVTTL I/Os. The
Virtex? series of FPGAs and the Spartan?-II family of FPGAs have many features, such as
SelectI/O? resource and the Clock Delay Lock Loop, that make it easy to interface to high
2 H  j, V# X# B, ~0 k! dspeed Synchronous DRAMs. This application note describes the design and implementation of
% `) _! G$ N/ f5 K; k& w0 aa synthesizable, parameterizable, flexible, auto-placed-and-routed synchronous DRAM
' y, h2 r9 y) dcontroller in the Virtex FPGA family. The design can also be implemented with a Spartan-II
4 B# K5 w! Y" @; M! t) sdevice. A 32-bit wide data interface version can run up to 125 MHz when automatically placed
and routed in a Virtex -6 speed grade device. Hand placed versions of the design can run even
7 e( S2 Z# a7 G! K5 H/ B0 Mfaster.

Hh0203

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Abricy

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xuzwg

学习中，谢谢分享

fish1352

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